74VCX16721MTD Fairchild Semiconductor, 74VCX16721MTD Datasheet
74VCX16721MTD
Specifications of 74VCX16721MTD
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74VCX16721MTD Summary of contents
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... CMOS power dissipation. Ordering Code: Order Number Package Number 74VCX16721MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...
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Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table D –D CLK HIGH Voltage Level L ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 3) 0. Input Diode Current ( Output ...
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DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC Note ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX C t Propagation Delay C PHL t PLH C t Output Enable Time C PZL t PZH C t Output Disable Time C PLZ t PHZ C t Setup ...
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Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL V Quiet Output Dynamic Valley V OHV OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT ...
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AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...
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AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...