24lc1025t-i-sm Microchip Technology Inc., 24lc1025t-i-sm Datasheet - Page 11

no-image

24lc1025t-i-sm

Manufacturer Part Number
24lc1025t-i-sm
Description
1024k I2c Cmos Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet
8.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
The 24XX1025 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX1025 issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX1025 discontinues transmission (Figure 8-1).
FIGURE 8-1:
© 2007 Microchip Technology Inc.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
READ OPERATION
Current Address Read
S
S
T
A
R
T
1
0
1
Control
Byte
0 B A A 1
CURRENT ADDRESS
READ
0 1 0
A
C
K
24AA1025/24LC1025/24FC1025
Data
Byte
N
O
C
A
K
Preliminary
S
T
O
P
P
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX1025 as part of a write operation (R/W bit set to
0). After the word address is sent, the master gener-
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. Then, the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX1025 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX1025 to discontinue
transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24XX1025 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX1025 to trans-
mit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX1025 contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows half the
memory contents to be serially read during one opera-
tion. Sequential read address boundaries are 0000h to
FFFFh and 10000h to 1FFFFh. The internal Address
Pointer will automatically roll over from address FFFF
to address 0000 if the master acknowledges the byte
received from the array address, 1FFFF. The internal
address counter will automatically roll over from
address 1FFFFh to address 10000h if the master
acknowledges the byte received from the array
address, 1FFFFh.
Random Read
Sequential Read
DS21941E-page 11

Related parts for 24lc1025t-i-sm