25lc040a Microchip Technology Inc., 25lc040a Datasheet - Page 10

• Manufacturer Part Number: 25lc040a
• Description: 4k Spi Bus Serial Eeprom
• Manufacturer: Microchip Technology Inc.

25AA040A/25LC040A
2.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX040A is busy with a write operation. When set to
a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
DS21827E-page 10
W/R = writable/readable. R = read-only.
SCK
1
CS
SO
’, a write is in progress, when set to a ‘
X
7
–
SI
Read Status Register Instruction
(RDSR)
6
–
X
0
5
–
X
0
STATUS REGISTER
X
4
–
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
1
W/R
BP1
High-impedance
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS Register
10
5
11
4
© 2007 Microchip Technology Inc.
12
3
13
2
14
1
15
0