at49bv802a ATMEL Corporation, at49bv802a Datasheet - Page 13

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at49bv802a

Manufacturer Part Number
at49bv802a
Description
8-megabit 512k X 16/ 1m X 8 3-volt Only Flash Memory
Manufacturer
ATMEL Corporation
Datasheet

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6. Command Definition Table
Notes:
3405E–FLASH–2/07
Command
Sequence
Read
Chip Erase
Sector Erase
Byte/Word Program
Enter Single Pulse
Program Mode
Single Pulse
Byte/Word Program
Sector Lockdown
Erase/Program
Suspend
Erase/Program
Resume
Product ID Entry
Product ID Exit
Product ID Exit
Program Protection
Register
Lock Protection
Register – Block B
Status of Block B
Protection
Set Configuration
Register
CFI Query
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A18 through A11
are don’t care in the word mode. Address A18 through A11 and A-1 are don’t care in the byte mode.
for details).
cycled.
(5)
(5)
Cycles
Bus
1
6
6
4
6
1
6
1
1
3
3
1
4
4
4
4
1
Addr
Addr
Addr
XXX
XXX
XXX
X55
555
555
555
555
555
555
555
555
555
555
555
1st Bus
Cycle
Data
D
F0
D
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B0
30
98
OUT
IN
(8)
AAA
AAA
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
2nd Bus
Cycle
(2)
(2)
Data
55
55
55
55
55
55
55
55
55
55
55
Addr
555
555
555
555
555
555
555
555
555
555
555
3rd Bus
Cycle
Data
F0
A0
C0
C0
D0
80
80
80
80
90
90
(8)
Addr
Addr
Addr
XXX
555
555
555
555
080
80
4th Bus
Cycle
00/01
D
Data
OUT
D
D
AA
AA
AA
AA
X0
IN
IN
(6)
(7)
AT49BV802A(T)
Addr
AAA
AAA
AAA
AAA
5th Bus
Cycle
Data
55
55
55
55
SA
SA
Addr
555
555
(3)(4)
(3)(4)
6th Bus
Cycle
15
Data
A0
10
30
60
-
16
13

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