at49lw040 ATMEL Corporation, at49lw040 Datasheet - Page 5

• Manufacturer Part Number: at49lw040
• Description: At49lw040 4-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

Table 1. Pin Description (Continued)
Firmware Hub
Interface (FWH)
3342A–FLASH–6/03
Symbol
GNDa
RFU
NC
RY/BY
Type
OUTPUT
SUPPLY
FWH
Table 2 lists the seven required signals used for the FWH interface.
Table 2. FWH Required Signal List
FWH[3:0]: The FWH[3:0] signal lines communicate address, control, and data informa-
tion over the LPC bus between a master and a peripheral. The information
communicated are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), trans-
fer direction (read/write), address, data, wait states, DMA channel, and bus master
grant.
FWH4: FWH4 is used by the master to indicate the start of cycles and the termination of
cycles due to an abort or time-out condition. This signal is to be used be by peripherals
to know when to monitor the bus for a cycle.
The FWH4 signal is used as a general notification that the FWH[3:0] lines contain infor-
mation relative to the start or stop of a cycle, and that peripherals must monitor the bus
to determine whether the cycle is intended for them. The benefit to peripherals of FWH4
is, it allows them to enter lower power states internally.
When peripherals sample FWH4 active, they are to immediately stop driving the
FWH[3:0] signal lines on the next clock and monitor the bus for new cycle information.
RESET: RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low dese-
lects the memory, places output drivers in a high-impedance state, and turns off all
X
X
X
Signal
FWH[3:0]
FWH4
RST
CLK
Interface
A/A Mux
X
X
X
Peripheral
I/O
I
I
I
Direction
Name and Function
ANALOG GROUND: Should be tied to same plane as GND.
RESERVED FOR FUTURE USE: These pins are reserved for future
generations of this product and should be connected accordingly. These
pins may be left disconnected or driven. If they are driven, the voltage
levels should meet V
A/A Mux = I/O[7:4]
NO CONNECT: Pin may be driven or floated. If it is driven, the voltage
levels should meet V
TSOP package.
READY/BUSY: Valid only in A/A Mux Mode. This output pin is a reflection
of bit 7 in the status register. This pin is used to determine sector erase or
program completion.
Master
I/O
O
I
I
Description
Multiplexed command, address and data
Indicates start of a new cycle, termination of broken
cycle.
Reset: Same as PCI Reset on the master. The master
does not need this signal if it already has PCIRST on its
interface.
Clock: Same 33 MHz clock as PCI clock on the master.
Same clock phase with typical PCI skew. The master
does not need this signal if it already has PCICLK on its
interface.
IH
IH
and V
and V
IL
IL
. No connects appear only on the 40-lead
requirements.
AT49LW040
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