at49sn6416 ATMEL Corporation, at49sn6416 Datasheet - Page 6

• Manufacturer Part Number: at49sn6416
• Description: 64-megabit 4m X 16 Burst/page Mode 1.8-volt Flash Memory
• Manufacturer: ATMEL Corporation

3.8
3.9
3.10
3.10.1
3.10.2
3.10.3
6
Burst Suspend
Reset
Erase
AT49SN6416(T)
Chip Erase
Plane Erase
Sector Erase
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst oper-
ation if the system needs to use the Flash address and data bus for other purposes. Burst
accesses can be suspended during the initial latency (before data is received) or after the device
has output data. When a burst access is suspended, internal array sensing continues and any
previously latched internal data is retained.
Burst Suspend occurs when CE is asserted, the current address has been latched (either rising
edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted
when it is at V
Subsequent CLK edges resume the burst sequence where it left off.
Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal
reverts to a high-impedance state when OE is deasserted.
page 33.
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET pin halts the
present device operation and puts the outputs of the device in a high-impedance state. When a
high level is reasserted on the RESET pin, the device returns to read mode.
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
planes can be erased by using the Plane Erase command or individual sectors can be erased by
using the Sector Erase command.
Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset
during chip erase will stop the erase, but the data will be of an unknown state.
As an alternative to a full Chip Erase, the device is organized into four planes that can be individ-
ually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address
is valid at the second rising edge of WE will be erased. The Plane Erase command does not
alter the data in the protected sectors.
The device is organized into multiple sectors that can be individually erased. The Sector Erase
command is a two-bus cycle operation. The sector whose address is valid at the second rising
edge of WE will be erased provided the given sector has not been protected.
IH
or V
IL
. To resume the burst access, OE is reasserted and the CLK is restarted.
See “Burst Suspend Waveform” on
3464C–FLASH–2/05