is62lv12816bll Integrated Silicon Solution, Inc., is62lv12816bll Datasheet - Page 7

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is62lv12816bll

Manufacturer Part Number
is62lv12816bll
Description
128k X 16 Low Voltage, Ultra Low Power Cmos Static Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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AC WAVEFORMS
WRITE CYCLE NO. 1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
WRITE CYCLE SWITCHING CHARACTERISTICS
IS62LV12816BLL
Symbol
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
t
t
t
t
t
t
t
t
t
t
t
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
WC
SCE
AW
HA
SA
PWB
PWE
SD
HD
HZWE
LZWE
of the LB and UB inputs being in the LOW state.
and output loading specified in Figure 1.
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
ADDRESS
(3)
(3)
UB, LB
D
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
OUT
Parameter
WE
D
CE
IN
DATA UNDEFINED
(1,2)
t
SA
(CE Controlled, OE = HIGH or LOW)
t
HZWE
t
VALID ADDRESS
Min.
AW
t
t
55
50
50
45
45
25
0
0
0
5
PWE1
PWE2
t
t
-55
SCS
WC
t
PBW
Max.
30
HIGH-Z
(1,2)
(Over Operating Range)
t
SD
DATA
Min.
70
65
65
60
60
30
0
0
0
5
IN
VALID
-70
Max.
t
30
HD
t
LZWE
t
HA
Min.
100
80
80
80
80
40
0
0
0
5
-100
UB_CSWR1.eps
Max.
40
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
7
1
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