is42s16800-7tli Integrated Silicon Solution, Inc., is42s16800-7tli Datasheet - Page 6

• Manufacturer Part Number: is42s16800-7tli
• Description: 16m X 8, 8m X16 128mb Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

PIN FUNCTIONS
IS42S81600, IS42S16800
6
DQ
DQ
BA0, BA1
Symbol
A0-A11
DQML,
DQMH
DQM
V
CAS
CKE
0
RAS
V
CLK
WE
V
V
CS
-DQ
0
ddq
-DQ
ssq
dd
ss
7
15
or
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Input/Output
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Type
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address A0-
A9 (x8), or A0-A8 (x16); with A10 defining auto precharge) to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank se-
lected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to
OE in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data
can be written to the device. When DQML or DQMH is HIGH, input data is masked
and cannot be written to the device. For IS42S16800 only.
For IS42S81600 only.
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
V
V
V
V
ddq
dd
ssq
ss
is the device internal ground.
is the device internal power supply.
is the output buffer ground.
is the output buffer power supply.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
08/06/08