m58lw064c STMicroelectronics, m58lw064c Datasheet - Page 13

• Manufacturer Part Number: m58lw064c
• Description: 64 Mbit 4mb X16, Uniform Block, Burst 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

BUS OPERATIONS
There are six standard bus operations that control
the device. These are Address Latch, Bus Read,
Bus Write, Output Disable, Power-Down and
Standby. See
mary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Address Latch. Address latch operations input
valid addresses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, V
Enable High, V
ing edge of Address Latch.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the Common
Flash Interface and the Block Protection Status.
A valid bus operation involves setting the desired
address on the Address Inputs, applying a Low
signal, V
Latch Enable and keeping Write Enable High, V
The data read depends on the previous command
written to the memory (see Command Interface
section). See Figures 11, 12, 13,
AC Waveforms, and Tables 15, 16,
Read AC Characteristics, for details of when the
output becomes valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch addresses and input
data to be programmed.
Table 2. Bus Operations
Note: 1. X = Don’t Care V
Output Disable
Address Latch
2. Depends on G
Power-Down
Operation
Bus Read
Bus Write
Standby
IL
, to Chip Enable, Output Enable and
Table 2., Bus
IH
; the address is latched on the ris-
IL
or V
V
IH
V
V
V
V
E
X
IH
.
IL
IL
IL
IL
Operations, for a sum-
IL
and keeping Write
18
V
V
V
G
X
X
X
IH
IH
IL
and
17
19
and
V
V
V
V
W
X
X
IH
IH
IH
IL
Read
20
IH
.
RP
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
A valid Bus Write operation begins by setting the
desired address on the Address Inputs and setting
Latch Enable Low, V
latched by the Command Interface on the rising
edge of Chip Enable or Write Enable, whichever
occurs first. The Data Inputs/Outputs are latched
by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V
the Bus Write operation.
See Figures 14, 15,
forms, and Tables
istics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are
high impedance when the Output Enable is at V
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
independent of Chip Enable, Output Enable or
Write Enable.
Standby. Standby disables most of the internal
circuitry, allowing a substantial reduction of the
current consumption. The memory is in standby
when Chip Enable is at V
tion is reduced to the standby level I
outputs are set to high impedance, independently
from the Output Enable or Write Enable inputs.
If Chip Enable switches to V
erase operation, the device enters Standby mode
when finished.
V
V
V
DD2
L
X
X
X
IL
IL
IL
, and the outputs are high impedance,
Address
Address
Address
A1-A22
18
X
X
X
16
and 19, Write AC Character-
IL
. The Address Inputs are
and 17, Write AC Wave-
IH
. The power consump-
IH
Data Output or Hi-Z
during a program or
Data Output
DQ0-DQ15
Data Input
M58LW064C
High Z
High Z
High Z
DD1
IH
and the
, during
13/61
(2)
IH
.