m58lw064a STMicroelectronics, m58lw064a Datasheet - Page 21

• Manufacturer Part Number: m58lw064a
• Description: 64 Mbit X16 And X16/x32, Block Erase Low Voltage Flash Memories
• Manufacturer: STMicroelectronics

Clear Status Register Instruction (CLRS). The
Clear Status Register Instruction is given with the
command 50h at any address location. It is a reset
instruction that resets DQ5, DQ4 and DQ1 in the
Status Register to ’0’.
If an operation such as Block Erase, Write to Buff-
er and Program Block Protect or Block Unprotect
has failed, the P/E.C. will set DQ5, DQ4 or DQ1 to
’1’ depending on the failure detected (see Table
12, Status Register Definition). The Clear Status
Register Instruction must be given before restart-
ing any corrective Erase/Program Instruction. The
CLRS Instruction should be given also after an
Erase or Program Suspend Instruction failure or
before a Resume Instruction if the previous in-
struction has been detected to have failed. It is
also a software reset solution that may allow the
execution of several operations such as cumulat-
ed Erase or Block Protect operations of multiple
blocks. The Clear Status Register instruction is
valid when the P/E.C. is inactive or the device is in
a suspend mode and it is also valid independent of
the voltage V
Write to Buffer and Program Instruction (WB-
PR). The Write to Buffer and Program Instruction
is used to program the memory array. Up to 16
Words or 8 Double-Words can be loaded into the
Write Buffer and programmed into the device. The
Write to buffer and Program Instruction is com-
posed of three successive steps. The first step is
to give the Write to Buffer and Program command,
E8h with the selected memory Block Address
where the program operation should occur. The
Status Register DQ7 bit then indicates the ”buffer
available” status. If the write buffer is not available
(indicated by DQ7 = 0) then the software can ei-
ther continue monitoring DQ7 until it transitions to
1, or else re-try later by reloading first the WBPR
command, E8h, and then again monitoring the val-
ue of DQ7.
Once the ”write buffer available” condition is valid
(indicated by DQ7 = 1), the second step is to write
the block address again, along with the value N,
where N+1 is the number of Words (x16 organisa-
tion) or Double-Words (x32 organisation) to be
programmed.
In the third step, a sequence of N+1 write cycles
loads the addresses and data to the write buffer
(see boundary constraints below). The addresses
IH
or V
HH
applied on the RP input.
must lie between the starting address and the
starting address + (N+1).
The array must be programmed in 4 Word or 2
Double-Word blocks, which must be aligned with
an A2 = A1 = 0 starting address (or A2 = 0 for x32
organisation). Invalid data will be flagged and the
operation will abort with the status register bits
DQ4 and DQ5 set to 1.
The Confirm Command, D0h (the same as Erase/
Program Resume PER Instruction) needs to be
given immediately after the completion of the Write
to Buffer and Program Instruction. It represents
the last (that is the N+2) write operation.
The P/E.C. is enabled only if the whole previous
sequence is fully respected. Otherwise an Invalid
Command/Sequence error will be generated with
the Status Register DQ5 and DQ4 set to ’1’. For
additional Write to Buffer and Program operations,
after the initial input command the software can
check the availability of the write buffer by check-
ing DQ7 status from the Status Register.
If an error appears during a program sequence,
the device will stop its operation and DQ4 of the
Status Register will be set to ’1’ to indicate a pro-
gram failure. DQ5 will indicate if an error has been
detected during a Block Erase operation. If these
bits, DQ4 or DQ5 are set to ’1’, the Write to Buffer
and Program input command is not accepted by
the device until the status register has been
cleared.
Additionally, if the Block is protected and
V
Buffer and Program Instruction will not be accept-
ed by the device, and DQ4 and DQ1 of the status
register will be set to ’1’.
Block Protect Instruction (BP). The Block Pro-
tect Instruction BP uses a two-cycle write se-
quence. The first write cycle gives the command
60h at any address location. The second write cy-
cle gives the block address memory location to be
protected and the command 01h.
Block protection can be cleared with the BU In-
struction, which unprotects all blocks. Alternative-
ly, temporary unprotect can be achieved by raising
the RP input to V
throughout the Block Erase or Write to Buffer and
Program operations.
IH
< RP < V
HH
instead of RP = V
M58LW064A, M58LW064B
HH
and holding it at that level
HH
, the Write to
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