psd835g2 STMicroelectronics, psd835g2 Datasheet
psd835g2
Manufacturer Part Number
psd835g2
Description
Configurable Memory System On A Chip For 8-bit Microcontrollers
Manufacturer
STMicroelectronics
Datasheet
1.PSD835G2.pdf
(120 pages)
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Features
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February 2009
Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
Dual bank flash memories
– 4 Mbits of primary Flash memory
– 256 Kbits of secondary Flash memory with
– Concurrent operation: READ from one
64 Kbit of SRAM
52 reconfigurable I/O ports
Enhanced JTAG serial port
PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
– DPLD - user defined internal chip select
52 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
– Efficient manufacturing allow easy product
– Use low cost FlashLINK cable with PC
(8 uniform sectors, 64 Kbytes)
4 sectors
memory while erasing and writing the other
and 24 Rev 5 macrocells (IMCs)
decoding
outputs.
full-chip in-system programmability
testing and programming
4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM
Flash PSD, 5 V supply, for 8-bit MCUs
Rev 5
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Page register
– Internal page register that can be used to
Programmable power management
High endurance
– 100,000 Erase/WRITE cycles of Flash
– 1,000 Erase/Write cycles of PLD
– 15 year data retention
5 V±10% single supply voltage
Standby current as low as 50 µA
Memory speed
– 70 ns Flash memory and SRAM access
– 90 ns Flash memory and SRAM access
ECOPACK
expand the microcontroller address space
by a factor of 256
memory
time for V
time for V
®
CC
CC
package
= 4.5 to 5.5 V
= 4.5 to 5.5 V
LQFP80 (U)
PSD835G2
www.st.com
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