s-24c128ci-t8t1u3 Seiko Instruments Inc., s-24c128ci-t8t1u3 Datasheet
s-24c128ci-t8t1u3
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s-24c128ci-t8t1u3 Summary of contents
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... Package name 8-Pin SOP (JEDEC) 8-Pin TSSOP Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable ...
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... GND 4 Figure 1 S-24C128CI-J8T1U3 8-Pin TSSOP Top view GND 4 5 Figure 2 S-24C128CI-T8T1U3 2 2 PROM Pin No Symbol * VCC * SCL 4 GND 5 SDA SDA SCL VCC *1. All input pins have the CMOS structure. Do not set the input pins in high impedance during operation ...
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... Serial Clock Controller LOAD COMP LOAD INC Address Counter Y Decoder D OUT Figure 3 Seiko Instruments Inc. 2-WIRE CMOS SERIAL E S-24C128C VCC WP GND Voltage Detector High-Voltage Generator Data Register Memory Cell Array X Decoder Selector Data Output ACK Output Controller 2 PROM 3 ...
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... Input voltage Output voltage Operation ambient temperature Storage temperature Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Item Power supply voltage ...
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... 0 500 Seiko Instruments Inc. 2-WIRE CMOS SERIAL 1 5 400 kHz Unit Min. Max 400 kHz Unit Min. Max. 4 Min. Max. Min. 4.5 4.5 1.0 1 ...
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... WS1 t WH1 t WS2 t WH2 t BUF HIGH LOW F t HD.DAT t AA Figure 5 Bus Timing Seiko Instruments Inc. Input pulse voltage Output reference voltage 0 0 Figure 4 I/O Waveform during AC Measurement Min. Max. 0 400 1.3 0.6 0.1 0.9 50 0.6 0.6 100 0 0.6 0 SU.DAT ...
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... Start Condition SCL SDA t WS1 WP (valid WS2 (invalid) Table 1 5 Symbol Min Acknowledgment Write data Signal D0 Figure 6 Write Cycle Timing Seiko Instruments Inc. 2-WIRE CMOS SERIAL E S-24C128C Unit Max. 5.0 ms Start Condition Stop Condition WH1 t WH2 2 PROM 7 ...
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... Wired-OR connection by pulling SCL (Serial Clock Input) Pin The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL clock, pay attention to the rising and falling time and comply with the specification. ...
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... Every operation begins from a start condition. 2. Stop Condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device enters standby mode. ...
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... SDA 4. Acknowledge The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA line to acknowledge the receipt of the 8-bit data. When an internal write cycle is in progress, the device does not generate an acknowledge. ...
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... The upper 4 bits of the device address are the “Device Code”, and are fixed to “1010”. In the S-24128C, successive 3 bits are the “Slave Address”. These 3 bits are used to identify a device on the system bus and is compared with the predetermined value which is defined by the address input pins (A2, A1, A0). ...
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... Write 6. 1 Byte Write When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, the S-24C128C acknowledges it. The S-24C128C then receives a upper 8-bit word address and responds with an acknowledge. And the S-24C128C receives a lower 8-bit word address and responds with an acknowledge ...
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... In the S-24C128C, the lower 6 bits of the word address are automatically incremented every time when the S- 24C128C receives 8-bit write data. If the size of the write data exceeds 64 bytes, the upper 8 bits of the word address remain unchanged, and the lower 6 bits are rolled over and the last 64-byte data that the S-24C128C received will be overwritten ...
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... If the WP pin changes during this time, the address data being written at this time is not guaranteed. Regarding the timing of write protect, refer to Figure not using the write protect, connect the WP pin to GND or set it open. The write protect is valid in the range of operation power supply voltage. ...
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... That is, if the S-24C128C does not generate an acknowledgment signal, the write cycle is in progress and if the S-24C128C generates an acknowledgment signal, the write cycle has been completed recommended to use the read instruction “1” as the read / write instruction code transmitted by the master device. ...
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... Attention should be paid to the following point on the recognition of the address pointer in the S-24C128C. In Read, the memory address counter in the S-24C128C is automatically incremented after output of the 8th bit of the data. In Write, on the other hand, the upper bits of the memory address (the upper bits of the word *1 address ) are left unchanged and are not incremented ...
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... That is, when the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the S-24C128C in synchronous to the SCL clock ...
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... S-24C128C 7. 3 Sequential Read When the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition both in current address read and random read, it responds with an acknowledge. When an 8-bit data is output from the S-24C128C synchronous to the SCL clock, the address counter is automatically incremented ...
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... Its detection and release voltages are 1.20 V typ. (Refer to Figure 19). The S-24C128C cancels Write by detecting a low power supply voltage when it receives a stop condition. In the data trasmission and the Write operation, data in the address written during the low power supply voltage is not assurable. ...
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... The S-24C128C cannot transmit normally without using a pull-up resistor. In case that the SCL input pin of the S-24C128C is connected to the Nch open drain output pin of the master device, connect the SCL pin with a pull-up resistor. As well, in case the SCL input pin of the S-24C128C is connected to the tri-state output pin of the master device, connect the SCL pin with a pull-up resistor in order not to set it in high impedance ...
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... Rev.2.0 _00_H WP A0, A1, A2 2-WIRE CMOS SERIAL E Figure 22 WP Pin Figure 23 A0, A1, A2 Pins Seiko Instruments Inc. 2 PROM S-24C128C 21 ...
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... S-24C128C. How to reset is shown below. [How to reset S-24C128C] The S-24C128C is able to be reset by a start and stop instructions. When the S-24C128C is reading data “0” outputting the acknowledgment signal, outputs “0” to the SDA line. In this status, the master device cannot output an instruction to the SDA line ...
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... V (Max.) 0.2 V INIT * means there is no difference in potential between the VCC pin and the GND pin of the S-24C128C. * the time required to initialize the S-24C128C. No instructions are accepted during this time. INIT = 200 ms seen in Figure 26. The power supply voltage ...
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... The voltage drops due to power off while the S-24C128C is being accessed. Even if the master device is reset due to the low power voltage, the S-24C128C may malfunction unless the power-on-clear operation conditions of S-24C128C are satisfied. When not using this rise time seen in Figure 26, adjust the phase (reset) to reset the internal circuit in the S- 24C128C normally. 24 ...
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... Rev.2.0 _00_H 5. 2 Initialization time The S-24C128C initializes at the same time when the power supply voltage is raised. Input instructions to the S-24C128C after initialization. S-24C128C does not accept any instruction during initialization. Figure 27 shows the initialization time of the S-24C128C. Initialization Time (t ) Max. ...
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... The S-24C128C may error if it does not recognize a start / stop condition correctly during transmission recommended to set the delay time of 0.3 s minimum from a falling edge of SCL for the SDA. This is to prevent S-24C128C from going in a start / stop condition due to the time lag caused by the load of the bus line. ...
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... By a start condition, users are able to cancel command which is being input. However, adjust the phase while the S-24C128C is outputting “L” because users are not able to input a start condition. When users cancel the command, there may be a case that the address will not be identified. Use random read for the read operation, not current address read. ...
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... Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. ● SII claims no responsibility for any and all disputes arising out connection with any infringement of the products including this IC upon patents owned by a third party. ...
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... Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc ...