w27c512 Winbond Electronics Corp America, w27c512 Datasheet - Page 2

• Manufacturer Part Number: w27c512
• Description: 64k X 8 Electrically Erasable Eprom
• Manufacturer: Winbond Electronics Corp America

FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE/V
to the output pins. When addresses are stable, the address access time (T
from CE to output (T
if T
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when OE/V
low, and all other address pins low and data input pins high. Pulsing CE low starts the erase
operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if V
V
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when OE /V
(12V), V
desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if OE /V
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the
CE and OE/V
CE
ACC
(3.75V), CE low, and OE/V
and T
CC
= V
CE
PP
CP
timings are met.
pins, the W27C512 may have common inputs.
(5V), the address pins equal the desired addresses, and the input pins equal the
CE
), and data are available at the outputs T
PP
low.
PP
is raised to V
- 2 -
PE
(14V), V
PP
controls the output buffer to gate data
CC
OE
after the falling edge of OE/V
= V
CE
(5V), A9 = V
ACC
PP
) is equal to the delay
low and CE low.
PP
W27C512
is raised to V
PE
(14V), A0
CC
PP
PP
=
,