nsbmc290 National Semiconductor Corporation, nsbmc290 Datasheet - Page 9

• Manufacturer Part Number: nsbmc290
• Description: Burst Mode Memory Controller
• Manufacturer: National Semiconductor Corporation

Functional Description
INTERCONNECT DETAILS
The NSBMC290 may be applied in designs where instruc-
tion and data memories are separated or in designs where
a single memory space is used for both instruction and data
In split instruction data designs the control signals for the
address space not required are simply pulled up to V
levels and not connected to the corresponding local chan-
nel signals
For mixed instruction and data designs all local channel
signals must be connected Tables V and VI detail the con-
trol signal sets required for the NSBMC290 to control the
corresponding address spaces It is recommended that all
control signals be connected and that instruction and data
space segregation be done via software allocation and or
use of the Am29000 internal Translation Look-Aside Buffer
TABLE VI Control Signal Set Unique to Data Accesses
Input
Output
Buffer Control
Input
Output
Buffer Control
Signal Type
Signal Type
TABLE V Control Signal Set Unique
to Instruction Accesses
IREQ IBREQ IREQT PIA
IBACK IRDY
IBTXA IBTXB IBTX BANKB A
DREQ DBREQ DREQT 1 0
OPT 2 0 PDA
DBACK DRDY
DBCEA B DBCE DBTXA B
DBTX BANKB A
Signal Names
Signal Names
(Continued)
CC
9
Typical Application
SYSTEM IMPLEMENTATION AND DESIGN
The ease with which the NSBMC290 may be integrated into
a system design is illustrated in the diagram in Figure 2 The
system shown supports an Am29000 with between 2 MB
and 32 MB of memory (depending on the storage devices
selected) managed by a single NSBMC290 This specific
example accommodates 256k x 1 1 MB x 1 or 4 MB x 1
devices
In a minimal system configuration only one NSBMC290 is
required This is because the NSBMC290 manages both in-
struction and data access to a memory block However with
a single memory block instruction and data accesses can-
not be overlapped and the number of burst access restarts
is a function of the way in which the software is designed It
is therefore difficult to predict performance degradation
If maximum performance is required the addition of one or
more NSBMC290s is an effective solution Our bench marks
indicate that for systems with physically separated instruc-
tion and data space performance is degraded by approxi-
mately 5% over the theoretical rate achieved in system de-
signs employing high speed static RAMs The device count
and cost of these solutions however differ by at least a
factor of 6
With the exception of data buffers external components are
not required except to terminate the address and control
lines to the memory array The use of passive components
arranged in a serial or parallel terminating network is a sim-
ple but effective method of implementing this requirement