lm5022mme National Semiconductor Corporation, lm5022mme Datasheet - Page 16

• Manufacturer Part Number: lm5022mme
• Description: 60v Low Side Controller For Boost And Sepic
• Manufacturer: National Semiconductor Corporation

www.national.com
The single pole causes a roll-off in the gain of -20 dB/decade
at lower frequency. The combination of the RHP zero and
sampling double pole maintain the slope out to beyond the
switching frequency. The phase tends towards -90° at lower
frequency but then increases to -180° and beyond from the
RHP zero and the sampling double pole. The effect of the
ESR zero is not seen because its frequency is several
decades above the switching frequency. The combination of
increasing gain and decreasing phase makes converters with
RHP zeroes difficult to compensate. Setting the overall con-
trol loop bandwidth to 1/3 to 1/10 of the RHP zero frequency
minimizes these negative effects, but requires a compromise
in the control loop bandwidth. If this loop were left uncom-
pensated, the bandwidth would be 89 kHz and the phase
margin -54°. The converter would oscillate, and therefore is
compensated using the error amplifier and a few passive
components.
The transfer function of the compensation block, G
derived by treating the error amplifier as an inverting op-amp
with input impedance Z
majority of applications will require a Type II, or two-pole one-
zero amplifier, shown in Figure 7. The LaPlace domain trans-
fer function for this Type II network is given by the following:
Many techniques exist for selecting the compensation com-
ponent values. The following method is based upon setting
the mid-band gain of the error amplifier transfer function first
and then positioning the compensation zero and pole:
1.
2.
Determine the desired control loop bandwidth: The
control loop bandwidth, f
control loop gain (H = G
this example, a low bandwidth of 10 kHz, or
approximately 1/6th of the RHP zero frequency, is
chosen because of the wide variation in input voltage.
Determine the gain of the power stage at f
value, A, can be read graphically from the gain plot of
G
‘2πf
approximately 16 dB.
PS
0dB
FIGURE 8. Power Stage Gain and Phase
or calculated by replacing the ‘s’ terms in G
’. For this example the gain at 10 kHz is
I
and feedback impedance Z
PS
0dB
x G
, is the point at which the total
EA
) is equal to 0 dB. For
20212297
0dB
EA
, can be
PS
: This
F
. The
with
16
3.
4.
5.
6.
7.
8.
9.
10. Plug the closest 1% tolerance values for R
11. Plot or evaluate the actual error amplifier transfer
Calculate the negative of A and convert it to a linear
gain: By setting the mid-band gain of the error amplifier
to the negative of the power stage gain at f
loop gain will equal 0 dB at that frequency. For this
example, -16 dB = 0.15V/V.
Select the resistance of the top feedback divider
resistor R
a resistance between 10 kΩ and 100 kΩ will lead to
practical values of R1, C1 and C2. For this example,
R
Set R1 = A x R
= 3 kΩ
Select a frequency for the compensation zero, f
The suggested placement for this zero is at the low
frequency pole of the power stage, f
this example, f
Set
For this example, C2 = 125 nF
Select a frequency for the compensation pole, f
The suggested placement for this pole is at one-fifth of
the switching frequency. For this example, f
Set
For this example, C1 = 530 pF
then the closest 10% values for C1 and C2 into G
and model the error amp: The open-loop gain and
bandwidth of the LM5022’s internal error amplifier are 75
dB and 4 MHz, respectively. Their effect on G
modeled using the following expression:
A
approximately 5600V/V. C1 = 560 pF 10%, C2 = 120 nF
10%, R1 = 3.01 kΩ 1%
function:
DC
FB2
is a linear gain, the linear equivalent of 75 dB is
= 20 kΩ 1%.
FB2
: This value is arbitrary, however selecting
Z1
FB2
= f
: For this example: R1 = 0.15 x 20000
LFP
= 423Hz
LFP
= ωLFP / 2π. For
0dB
P1
, the control
FB2
= 100 kHz
EA
and R1,
can be
Z1
P1
EA
:
: