lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 13

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

Power Up Sequence
The VIN operating range of the LM5066 is 10V to 80V, with a
transient capability to 100V. Referring to
2, as the voltage at VIN initially increases, the external N-
channel MOSFET (Q
down current at the GATE pin. The strong pull-down current
at the GATE pin prevents an inadvertent turn-on as the
MOSFET’s gate-to-drain (Miller) capacitance is charged. Ad-
ditionally, the TIMER pin is initially held at ground. When the
V
gins. During the insertion time, the capacitor at the TIMER pin
(C
by a 4.2 mA pull-down current at the GATE pin regardless of
the input voltage. The insertion time delay allows ringing and
transients at V
time ends when the TIMER pin voltage reaches 3.9V. C
then quickly discharged by an internal 1.5 mA pull-down cur-
rent. The GATE pin then switches on Q
the UVLO threshold. If V
end of the insertion time, Q
sources 20 µA to charge the gate capacitance of Q
maximum voltage from the gate to source of the Q
by an internal 16.5V zener diode.
IN
T
) is charged by a 4.8 µA current source, and Q
voltage reaches the POR threshold the insertion time be-
IN
to settle before Q
1
) is held off by an internal 115 mA pull-
IN
is above the UVLO threshold at the
1
the GATE pin charge pump
1
is enabled. The insertion
1
Figure 1
when V
FIGURE 1. Typical Application Circuit
1
and
IN
1
is held off
is limited
exceeds
Figure
1
. The
T
is
13
As the voltage at the OUT pin increases, the LM5066 monitors
the drain current and power dissipation of MOSFET Q
rush current limiting and/or power limiting circuits actively
control the current delivered to the load. During the in-rush
limiting interval (t
current source charges C
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 3.9V, the 75 µA current source
is switched off, and C
current sink (t
engage unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9V before in-rush current
limiting or power limiting ceases during t
and Q
a complete description of the fault mode.
The LM5066 will assert the SMBA pin after the input voltage
has exceeded its POR threshold to indicate that the volatile
memory and device settings are in their default state. The
CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC
register (80h) indicates default configuration of warning
thresholds and device operation and will remain high until a
CLEAR_FAULTS command is received.
1
is turned off. See the Fault Timer & Restart section for
3
in
2
Figure
in
Figure
T
is discharged by the internal 2.5 µA
2). The in-rush limiting will no longer
T
. If Q
2) an internal 75 µA fault timer
1
’s power dissipation and the
2
, a fault is declared
30115911
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1
. In-