lm5041sdx National Semiconductor Corporation, lm5041sdx Datasheet - Page 3

• Manufacturer Part Number: lm5041sdx
• Description: Cascaded Pwm Controller
• Manufacturer: National Semiconductor Corporation

Pin Description
DAP
LLP
PIN
10
11
12
13
14
15
16
9
RT / SYNC
NAME
PGND
AGND
UVLO
PULL
TIME
SUB
CS
SS
Output of the push-pull drivers
Power ground
Analog ground
Current sense input
Soft-start control
Push-Pull overlap and dead time control
Oscillator timing resistor pin and sync
Line Under-Voltage Shutdown
Die substrate
(Continued)
DESCRIPTION
3
Output of the push-pull gate driver. Output capability
of 1.5A peak.
Connect directly to analog ground.
Connect directly to power ground.
Current sense input to the PWM comparator (CM
control). There is a 50ns leading edge blanking on
this pin. Using separate dedicated comparators, if
CS exceeds 0.5V the outputs will go into cycle by
cycle current limit. If CS exceeds 0.6V the outputs
will be disabled and a soft-start commenced.
An external capacitor and an internal 10uA current
source, set the soft-start ramp. The controller will
enter a low power state if the SS pin is below the
shutdown threshold of 0.45V
An external resistor (R
dead time for the push-pull outputs. A resistor
connected between TIME and GND produces
overlap. A resistor connected between TIME and
REF produces dead time.
An external resistor sets the oscillator frequency.
This pin will also accept an external oscillator.
An external divider from the power converter source
sets the shutdown levels. Threshold of operation
equals 2.5V. Hysteresis is set by a switched internal
current source (20µA).
The exposed die attach pad on the LLP package
should be connected to a PCB thermal pad at
ground potential. For additional information on using
National Semiconductor’s No Pull Back LLP
package, please refer to LLP Application Note
AN-1187.
APPLICATION INFORMATION
SET
) sets the overlap time or
www.national.com