x9522v20iz-bt1 Intersil Corporation, x9522v20iz-bt1 Datasheet - Page 10

• Manufacturer Part Number: x9522v20iz-bt1
• Description: Triple Dcp, Dual Voltage Monitors
• Manufacturer: Intersil Corporation

A detailed description of the function of each of the
CONSTAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9522 device. This bit must first be enabled before
ANY write operation (to DCPs, or the CONSTAT regis-
ter). If the WEL bit is not first enabled, then ANY pro-
ceeding (volatile or nonvolatile) write operation to DCPs,
or the CONSTAT register, is aborted and no ACKNOWL-
EDGE is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis-
ter) or until the X9522 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 12).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9522. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
NOTE: Bits belled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
CS7
Figure 11. CONSTAT Register Format
0
DWLK
RWEL
V2OS
V3OS
Bit(s)
WEL
CS7
CS4
CS0
V2OS
CS6
V3OS
CS5
Always set to “0” (RESERVED)
Always set to “0” (RESERVED)
Register Write Enable Latch bit
Always set to “0” (RESERVED)
CS4
0
Sets the DCP Write Lock
Write Enable Latch bit
V2 Output Status flag
V3 Output Status flag
10
DWLK
CS3
NV
Description
CS2
RWEL
CS1
WEL
CS0
0
X9522
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state,
in one of two cases:
—After a successful write operation to any bits of
—When the X9522 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
When the DCP Write Lock bit of the CONSTAT register
is set to “1”, then the “wiper position” of the DCPs can-
not be changed - i.e. DCP write operations cannot be
conducted:
The factory default setting for this bit is DWLK = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9522 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x=2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre-
sponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
the CONSTAT register has been completed (See
Figure 12).
DWLK
0
1
DCP Write Operation Permissible
YES (Default)
NO
January 3, 2006
FN8208.1