hip4081ip Intersil Corporation, hip4081ip Datasheet - Page 15

• Manufacturer Part Number: hip4081ip
• Description: 80v/2.5a Peak, High Frequency Full Bridge Fet Driver
• Manufacturer: Intersil Corporation

Supplemental Information for HIP4080
and HIP4081 Power Application
The HIP4080 and HIP4081 H-Bridge Driver ICs require
external circuitry to assure reliable start-up conditions of the
upper drivers. If not addressed in the application, the
H-bridge power MOSFETs may be exposed to shoot-
through current, possibly leading to MOSFET failure. Follow-
ing the instructions below will result in reliable start-up.
HIP4081
The HIP4081 has four inputs, one for each output. Outputs
ALO and BLO are directly controlled by input ALI and BLI.
By holding ALI and BLI low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 33. As the V
up, the DIS voltage is below its input threshold of 1.7V due to
the R1/R2 resistor divider. When V
mately 9V to 10V, DIS becomes greater than the input
threshold and the chip disables all outputs. It is critical that
ALI and BLI be held low prior to DIS reaching its threshold
ENABLE
8.2V
56K
3.3K
15K
V
R1
R2
DD
56K
DD
/V
10
1 BHB
2
3
4
5
6
7
8
9
CC
2N3906
DD
BHI
DIS
V
BLI
ALI
AHI
HDEL
LDEL
AHB
100K
SS
supply ramps from zero
/V
V
DD
CC
ENABLE
BHO
AHO
BHS
BLO
ALO
AHS
exceeds approxi-
BLS
ALS
V
V
DD
CC
20
19
18
17
16
15
14
13
12
11
HIP4081
FIGURE 33.
FIGURE 34.
0.1 F
100K
15
ENABLE
level of 1.7V while V
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
HIP4080
The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a com-
parator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.
However, keeping both lower MOSFETs off can be accom-
plished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 34. Pulling
LDEL to V
through the input comparator and will keep the lower MOS-
FETs off. With the lower MOSFETs off and the chip enabled,
i.e., DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+/IN- switch a full cycle while LDEL
is held high, to avoid shoot-through. This start-up procedure
can be initiated by the supply voltage and/or the chip enable
command by the circuit in Figure 33.
V
DD
DD
3.3K
15K
will indefinitely delay the lower turn-on delays
R1
R2
RDEL
RDEL
DD
10
/V
10
1 BHB
2
3
4
5
6
7
8
9
1 BHB
2
3
4
5
6
7
8
9
CC
BHI
DIS
V
BLI
ALI
AHI
HDEL
LDEL
AHB
HEN
DIS
V
OUT
IN+
IN-
HDEL
LDEL
AHB
SS
SS
is ramping up, so that shoot
BHO
AHO
BHS
BLO
ALO
AHS
BHO
AHO
BLS
ALS
V
V
BHS
BLO
ALO
AHS
BLS
V
V
ALS
DD
CC
DD
CC
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11