ml4827cs-2 Fairchild Semiconductor, ml4827cs-2 Datasheet - Page 10

• Manufacturer Part Number: ml4827cs-2
• Description: Fault-protected Pfc And Pwm Controller Combo
• Manufacturer: Fairchild Semiconductor

ML4827
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4827 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC sec-
tion of the device, from which it also derives its basic timing.
The PWM is capable of current-mode or voltage mode oper-
ation. In current-mode applications, the PWM ramp (RAMP
2) is usually derived directly from a current sensing resistor
or current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the con-
verter’s output stage. DC I
cycle current limiting, is typically connected to RAMP 2 in
such applications. For voltage-mode operation or certain
specialized applications, RAMP 2 can be connected to a sep-
arate RC timing network to generate a voltage ramp against
which V
use of voltage feedforward from the PFC buss can assist in
line regulation accuracy and response. As in current mode
operation, the DC I
overcurrent protection.
No voltage error amplifier is included in the PWM stage of
the ML4827, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP 2 input which allows V
to command a zero percent duty cycle for input voltages
below 1.25V.
Maximum Duty Cycle
In the ML4827-1, the maximum duty cycle of the PWM sec-
tion is limited to 50% for ease of use and design. In the case
of the ML4827-2, the maximum duty cycle of the PWM sec-
tion is extended to 70% (typical) for enhanced utilization of
the inductor. Operation at 70% duty cycle requires special
care in circuit design to avoid volt-second imbalances, and/
or high-voltage damage to the PWM switch transistor(s).
Using the ML4827-2
The ML4827-2’s higher PWM duty cycle offers several
design advantages that skilled power supply and magnetics
engineers can take advantage of, including:
• Reduced RMS and peak PWM switch currents
• Reduced RMS and peak PWM transformer currents
• Easier RFI/EMI filtering due to lower peak currents
These reduced currents can result in cost savings by allowing
smaller PWM transformer primary windings and fewer turns
on forward converter reset windings. Long duty cycles, by
allowing greater utilization of the PFC’s stored charge, can
also lower the cost of PFC bus capacitors while still offering
long “hold-up” times.
10
DC
will be compared. Under these conditions, the
LIMIT
input would is used for output stage
LIMIT
, which provides cycle-by-
DC
NOTE: during the time when the PWM switch is off (the
reset or flyback periods), increasing duty cycles will result in
rapidly increasing peak voltages across the switch. This
result of high PWM duty cycles requires greater care be used
in circuit design. Relevant design issues include:
• Higher voltage (>1000V) PWM switches
• More carefully designed and tested PWM transformers
• Clamps and/or snubbers when needed
Also, slope compensation will be required in most current
mode PWM designs.
For those who want to approach the limits of attainable per-
formance (most commonly high-volume, low-cost supplies),
the ML4827-2’s 70% maximum PWM duty cycle offers sev-
eral desirable design capabilities. Using a 70% duty cycle
makes it essential to perform a careful magnetics design and
component stress analysis before finalizing designs with the
ML4827-2.
The ML4827-2: Special Considerations for
High Duty Cycles
The use of the ML4827-1, especially with the type of PWM
output stage shown in the Application Circuit of Figure 6, is
straightforward due to the limitation of the PWM duty cyle
to 50% maximum. In fact, one of the advantages of the “two-
transistor single-ended forward converter” shown in Figure 6
is that it will necessarily reset the core, with no additional
winding required, as long as the core does not go into satura-
tion during the topology's maximum permissible 50% duty
cycle.
For the “-2” version of the ML4827, the maximum duty
cycle (δ) of the PWM is nominally 70%. As the two-transis-
tor single-ended forward converter cannot be used at duty
cycles greater than 50%, high-δ applications require the use
of either a single-transistor forward converter (with a trans-
former reset winding), or a flyback output stage. In either
case, special concerns arise regarding the peak voltage
appearing on the PWM switch transistor, the PWM output
transformer, and associated power components as the duty
cycle increases. For any output stage topology, the available
on-time (core “set” time) is (1/f
for the core of the PWM output transformer is (1/f
(1–δ). This means that the magnetizing inductance of the
core charges for a period of (1/f
pletely discharged during a period of (1/f
ratio of these two periods, multiplied by the maximum value
of the PFC’s V
the PWM output transistor must be rated. Frequently, the
design of the tranformer’s reset winding, and/or of the output
transistor’s snubbers or clamps, require an additional voltage
margin of 100V to 200V.
BUSS
, yields the minimum voltage for which
PWM
PWM
PRODUCT SPECIFICATION
) x δ, while the reset time
) x δ, and must be com-
PWM
REV. 1.0.1 6/27/01
) x (1–δ). The
PWM
) x