ml4833 Microsemi Corporation, ml4833 Datasheet - Page 6

• Manufacturer Part Number: ml4833
• Description: Electronic Dimming Ballast Controller
• Manufacturer: Microsemi Corporation

ML4833
FUNCTIONAL DESCRIPTION
OVERVIEW
The ML4833 consists of peak current controlled
continuous boost power factor front end section with a
flexible ballast control section. Start-up and lamp-out
retry timing are controlled by the selection of external
timing components, allowing for control of a wide variety
of different lamp types. The ballast section controls the
lamp power using frequency modulation (FM) with
additional programmability provided to adjust the VCO
frequency range. This allows for the IC to be used with a
variety of different output networks. Figure 1 depicts a
detailed block diagram of ML4833.
POWER FACTOR SECTION
The ML4833 power factor section is a peak current
sensing boost mode PFC control circuit in which only
voltage loop compensation is needed. It is simpler than a
conventional average current control method. It consists
of a voltage error amplifier, a current sense amplifier (no
6
16
17
11
18
10
6
7
9
1
2
R
R
R
VCC
V
GND
PVFB/OVP
PEAO
C
PIFB
SET
T
X
REF
RAMP
/C
/C
T
X
THERMAL SHUTDOWN
2.75V
–1.0V
UNDER-VOLTAGE
REFOK
–
+
–
+
OVP
ILIM
2.5V
+
–
Figure 1. ML4833 Detailed Block Diagram
PREHEAT
TIMER
I
SENSE
AMPLIFIER
V TO I
R
S
Q
OSC
compensation is needed), an integrator, a comparator, and
a logic control block. In the boost topology, power factor
correction is achieved by sensing the output voltage and
the current flowing through the current sense resistor. Duty
cycle control is achieved by comparing the integrated
voltage signal of the error amplifier and the voltage
across R
Figure 2. Setting minimum input voltage for output
regulation can be achieved by selecting C
to equation 1.
OVERVOLTAGE PROTECTION AND INHIBIT
The OVP pin serves to protect the power circuit from
being subjected to excessive voltages if the load should
change suddenly (lamp removal). A divider from the high
voltage DC bus sets the OVP trip level. When the voltage
on PVFB/OVP exceeds 2.75V, the PFC transistor are
inhibited. The ballast section will continue to operate.
C
RAMP
CLK
PEAO
22
SENSE
K
MAX
(
. The duty cycle control timing is shown in
1
–
+
D Ts
T Q
)
+
–
1 1
.
s
1.25V
2
R
V
S
P
OUT
IN
Q
V
OUT
2
L
1
2
V
IN
+
–
+
–
(
1
RAMP
D Ts
1.0V
2.5V
INTERRUPT
)
PFC OUT
LFB OUT
LAMP FB
8
PDWN
OUT A
OUT B
PGND
R
SENSE
according
15
14
13
12
5
4
8
3
(1)