at91sam7se512 ATMEL Corporation, at91sam7se512 Datasheet
at91sam7se512
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at91sam7se512 Summary of contents
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... Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production • 32 Kbytes (AT91SAM7SE512/256 Kbytes (AT91SAM7SE32) of Internal High-speed SRAM, Single-cycle Access at Maximum Speed • One External Bus Interface (EBI) – ...
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... Fully Static Operation: – MHz at 1.8V and 85°C Worst Case Conditions – MHz at 1.65V and 85°C Worst Case Conditions • Available in a 128-lead LQFP Green Package 144-ball LFBGA RoHS-compliant Package AT91SAM7SE512/256/32 Preliminary 2 ® Infrared Modulation/Demodulation 6222ES–ATARM–04-Jan-08 ...
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... Atmel's AT91SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32-bit ARM7 • AT91SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM. • AT91SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM. • AT91SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM. ...
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... NPCS1 NPCS2 NPCS3 SPCK TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 ADTRG ADVREF AT91SAM7SE512/256/32 Preliminary 4 AT91SAM7SE512/256/32 Block Diagram Signal Description TDI ICE ARM7TDMI TDO JTAG TMS Processor SCAN TCK System Controller TST FIQ Memory Controller AIC Embedded Flash Controller ...
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... AT91SAM7SE512/256/32 Preliminary Summary 3. Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND ...
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... Timer Counter I/O Line B PWM0 - PWM3 PWM Channels MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 SPI Peripheral Chip Select 0 NPCS1-NPCS3 SPI Peripheral Chip Select AT91SAM7SE512/256/32 Preliminary 6 Active Type Level PIO I/O I/O I/O USB Device Port Analog Analog USART ...
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... AT91SAM7SE512/256/32 Preliminary Summary Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY ...
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... SDWE SDRAM Write Enable RAS - CAS Row and Column Signal NBS[3:0] Byte Mask Signals SDA10 SDRAM Address 10 Line Note: 1. Refer to Section 6. “/O Lines Considerations” on page AT91SAM7SE512/256/32 Preliminary 8 Active Type Level EBI for NAND Flash Support Output Low Output Low Output ...
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... AT91SAM7SE512/256/32 Preliminary Summary 4. Package The AT91SAM7SE512/256/32 is available in: • 128-lead LQFP package with a 0.5 mm lead pitch. • 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch 4.1 128-lead LQFP Package Outline Figure 4-1 description is given in the Mechanical Characteristics section of the full datasheet. ...
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... VDDCORE 55 24 PA8/PGMM0 56 25 PA7/PGMNVALID 57 26 PA6/PGMNOE 58 27 PA5/PGMRDY 59 28 PA4/PGMNCMD 60 29 PA3 61 30 PA2/PGMEN2 62 31 PA1/PGMEN1 63 32 PA0/PGMEN0 64 AT91SAM7SE512/256/32 Preliminary 10 PB31 65 PB30 66 TDO PB29 67 PB2 PB28 68 PB1 PB27 69 PB0 PB26 70 GND PB25 71 VDDIO PB24 72 VDDCORE PB23 73 NRST PB22 74 TST ...
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... AT91SAM7SE512/256/32 Preliminary Summary 4.3 144-ball LFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section. Figure 4-2. 6222ES–ATARM–04-Jan-08 shows the orientation of the 144-ball LFBGA package and a detailed mechanical 144-ball LFBGA Package Outline (Top View ...
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... PB11 F4 C5 PB15 F5 C6 PB19 F6 C7 PB21 F7 C8 PB27 F8 C9 PA6/PGMNOE F9 C10 PA5/PGMRDY F10 C11 PA2/PGMEN2 F11 C12 PA3 F12 AT91SAM7SE512/256/32 Preliminary 12 Signal Name Pin Signal Name VDDCORE G1 PC18 VDDCORE G2 PC16 PB2 G3 PC17 TDO G4 PC9 TDI G5 VDDIO PB17 G6 GND PB26 G7 GND ...
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... Power Consumption The AT91SAM7SE512/256/32 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current. ...
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... For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. shows the power schematics to be used for USB bus-powered systems. ...
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... AT91SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND. ...
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... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 300 mA. AT91SAM7SE512/256/32 Preliminary 16 6222ES–ATARM–04-Jan-08 ...
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... AT91SAM7SE512/256/32 Preliminary Summary 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V) • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction Fetch (F) – ...
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... External memory mapping, 512-Mbyte address space • 8-, or 16-bit Data Bus • Chip Select Lines • Multiple Access Modes supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank AT91SAM7SE512/256/32 Preliminary 18 ® Support 6222ES–ATARM–04-Jan-08 ...
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... AT91SAM7SE512/256/32 Preliminary Summary • Multiple device adaptability – Compliant with LCD Module – Compliant with PSRAM in synchronous operations – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – ...
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... One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements • Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest): AT91SAM7SE512/256/32 Preliminary 20 Receive DBGU ...
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... Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM (AT91SAM7SE512/256) – Single-cycle access at full speed • 8 Kbytes of Fast SRAM (AT91SAM7SE32) – Single-cycle access at full speed 6222ES– ...
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... MBytes 1,536 MBytes Undefined (Abort) 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7SE512/256/32 Preliminary 22 Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes Flash before Remap SRAM after Remap 0x000F FFFF 0x0010 0000 1 MBytes ...
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... SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.1.1.2 Internal ROM The AT91SAM7SE512/256/32 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA boot program. 8.1.1.3 Internal Flash • ...
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... Embedded Flash 8.1.2.1 Flash Overview The Flash of the AT91SAM7SE512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. It reads as 131,072 32-bit words. The Flash of the AT91SAM7SE256 is organized in 1024 pages (single plane) of 256 bytes. It reads as 65,536 32-bit words. The Flash of the AT91SAM7SE32 is organized in 256 pages (single plane) of 128 bytes. It reads as 8192 32-bit words ...
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... AT91SAM7SE512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes ...
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... The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low. • The Flash of the AT91SAM7SE512 is organized in 2048 pages of 256 bytes (dual plane). It reads as 131,072 32-bit words. ...
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... AT91SAM7SE512/256/32 Preliminary Summary ® 8.1.4 SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. • Communication via the DBGU supports a wide range of crystals from MHz via software auto-detection. • ...
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... Figure 9-1 on page 29 Figure 8-1 on page 22 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. AT91SAM7SE512/256/32 Preliminary 28 shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- 6222ES–ATARM–04-Jan-08 ...
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... AT91SAM7SE512/256/32 Preliminary Summary Figure 9-1. NRST XOUT PLLRC PA0-PA31 PB0-PB31 PC0-PC29 6222ES–ATARM–04-Jan-08 System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..18] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval ...
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... Brownout Detector and Power On Reset The AT91SAM7SE512/256/32 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the VDDCORE power supply. ...
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... AT91SAM7SE512/256/32 Preliminary Summary • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. 9.3 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • ...
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... Protect Mode – Easy debugging by preventing automatic operations • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt AT91SAM7SE512/256/32 Preliminary 32 Power Management Controller Block Diagram Processor Clock Controller ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x272A 0A40 (VERSION 0) for AT91SAM7SE512 – Chip ID is 0x272A 0940 (VERSION 0) for AT91SAM7SE256 – Chip ID is 0x2728 0340 (VERSION 0) for AT91SAM7SE32 9 ...
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... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). AT91SAM7SE512/256/32 Preliminary 34 6222ES–ATARM–04-Jan-08 ...
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... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Peripheral Identifiers The AT91SAM7SE512/256/32 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM7SE512/256/32. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multi- plex the I/O lines of the peripheral set. PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... AT91SAM7SE512/256/32 Preliminary Summary 10.4 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 MISO PA13 ...
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... PB21 PCK1 PB22 NPCS3 PB23 PWM0 PB24 PWM1 PB25 PWM2 PB26 TIOA2 PB27 TIOB2 PB28 TCLK1 PB29 TCLK2 PB30 NPCS2 PB31 PCK2 AT91SAM7SE512/256/32 Preliminary 38 Peripheral B Comments A0/NBS0 A1/NBS2 A10 A11 A12 A13 A14 A15 A16/BA0 A17/BA1 D16 ...
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... AT91SAM7SE512/256/32 Preliminary Summary 10.6 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 D8 PC9 D9 PC10 D10 PC11 D11 PC12 D12 PC13 D13 PC14 D14 PC15 D15 PC16 A18 PC17 A19 PC18 A20 ...
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... Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider AT91SAM7SE512/256/32 Preliminary 40 6222ES–ATARM–04-Jan-08 ...
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... AT91SAM7SE512/256/32 Preliminary Summary • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.11 Timer Counter • ...
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... Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Each analog input shared with digital signals AT91SAM7SE512/256/32 Preliminary 42 6222ES–ATARM–04-Jan-08 ...
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... AT91SAM7SE512/256/32 Preliminary Summary 11. Package Drawings Figure 11-1. 128-lead LQFP Package Drawing 6222ES–ATARM–04-Jan-08 43 ...
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... Figure 11-2. 144-ball LFBGA Package Drawing All dimensions are in mm AT91SAM7SE512/256/32 Preliminary 44 6222ES–ATARM–04-Jan-08 ...
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... AT91SAM7SE512/256/32 Preliminary Summary 12. Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7SE512-AU AT91SAM7SE256-AU AT91SAM7SE32-AU AT91SAM7SE512-CU AT91SAM7SE256-CU AT91SAM7SE32-CU 6222ES–ATARM–04-Jan-08 Package Package Type LQFP128 Green LQFP128 Green LQFP128 Green LFBGA144 Green LFBGA144 Green LFBGA144 Green Temperature Operating Range Industrial (-40°C to 85°C) Industrial (-40° ...
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... Overview”, updated AT91SAM7SE32 ...”reads as 8192 32-bit words.” Section 6. ”/O Lines Considerations”, updated 6222ES Section 10.11 ”Timer Counter”, .....the TC has two ouput compare and one input capture per channel. AT91SAM7SE512/256/32 Preliminary 46 ordering information code reference changed Section 6.3 ”Reset Pin”, Section 6.5 ”SDCK PDC priority list added Controller” ...
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... Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, DataFlash® , SAM-BA trademarks, others are trademarks of Atmel Corporation or its subsidiaries. ARM®, the ARM Powered® logo, ARM7TDMI®, Thumb® and others are registered trademarks or trademarks of ARM Limited. Other terms and product names may be trademarks of others. ...