lpc2926 NXP Semiconductors, lpc2926 Datasheet
lpc2926
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lpc2926 Summary of contents
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... ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial and communication markets. To optimize system power consumption, the LPC2926/2927/2929 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features and benefits ARM968E-S processor running at frequencies 125 MHz maximum ...
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... LQFP package. −40 °C to +85 °C ambient operating temperature range. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 © NXP B.V. 2010. All rights reserved ...
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... LPC2929FBD144 768 kB [1] Note that parts LPC2926, LPC2927 and LPC2929 are not fully pin compatible with parts LPC2917, LPC2919 and LPC2917/01, LPC2919/01. The Modulation and Sampling Control SubSystem (MSCSS) and timer blocks have a reduced pinout on the LPC2926/2927/2929. LPC2926_27_29 Product data sheet ...
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... PWM0/1/2/3 3.3 V ADC1 ADC0 QUADRATURE ENCODER CAN0/1 GLOBAL ACCEPTANCE FILTER UART/LIN0/1 I2C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2926/2927/2929 block diagram LPC2926_27_29 Product data sheet JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 8 kB SRAM ARM968E-S ...
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... Pin description 5.2.1 General description The LPC2926/2927/2929 uses five ports: port 0 with 32 pins, ports 1 and 2 with 28 pins each, port 3 with 16 pins, and port 5 with 2 pins. Port 4 is not used. The pin to which each function is assigned is controlled by the SFSP registers in the System Control Unit (SCU). ...
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... PWM1 MAT0 GPIO1, pin 24 PWM0 MAT0 GPIO1, pin 23 UART0 RXD All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Function 2 PWM2 CAP2 PWM3 CAP0 PWM1 MAT0 PWM1 MAT1 TIMER0 CAP2 ...
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... GPIO1, pin 11 SPI1 SCK GPIO1, pin 10 SPI1 SDI GPIO3, pin 12 SPI1 SCS0 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Function 2 USB_UP_LED TIMER1 CAP3, MSCSS PAUSE SPI0 SCS1 SPI0 SCS2 ...
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... SPI1 SCK 3.3 V power supply for I/O GPIO2, pin 8 CLK_OUT GPIO2, pin 9 USB_UP_LED All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Function 2 EXTINT5 EXTINT0 EXTINT1 LIN1 RXD/UART RXD LIN1 TXD/UART TXD ...
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... TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects boundary scan; pulled up internally. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Function 2 PWM3 MAT3 PWM3 MAT2 ...
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... GPIO2, pin 17 UART1 RXD 3.3 V power supply for I/O GPIO0, pin 18 ADC2 IN2 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Function 2 LIN0 TXD/UART TXD LIN0 RXD/UART TXD PWM1 MAT0 PWM1 MAT1 ...
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... USB pad. [3] Analog pad; analog I/O. [4] Analog I/O pad. 6. Functional description 6.1 Architectural overview The LPC2926/2927/2929 consists of: • An ARM968E-S processor with real-time emulation support • An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers • Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem). • ...
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... NXP Semiconductors The LPC2926/2927/2929 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB-to-APB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the APB side of the bridge, it continues even though the actual write may not yet have taken place ...
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... NXP Semiconductors 6.3 On-chip flash memory system The LPC2926/2927/2929 includes a 256 kB, 512 kB or 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished via the flash memory controller or the JTAG. The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated on the LPC2926/2927/2929 ...
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... ITCM/DTCM reserved 0x0040 8000 memory 32 kB DTCM 0x0040 0000 reserved 0x0000 8000 32 kB ITCM 0x0000 0000 Fig 3. LPC2926/2927/2929 memory map 0xFFFF FFFF 4 GB PCR/VIC control 0xFFFF 8000 reserved 0xF080 0000 DMA interface to TCM 0xF000 0000 reserved 0xE018 3000 ETB control ...
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... RST At activation of the RST pin the JTAGSEL pin is sensed as logic LOW. If this is the case the LPC2926/2927/2929 is assumed to be connected to debug hardware, and internal circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when running at LP_OSC speed is too low for the external debugging environment ...
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... Clocking strategy 6.7.1 Clock architecture The LPC2926/2927/2929 contains several different internal clock areas. Peripherals like Timers, SPI, UART, CAN and LIN have their own individual clock sources called base clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be unrelated in frequency and phase and can have different clock sources within the CGU ...
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... USB REGISTERS general subsytem SYSTEM CONTROL EVENT ROUTER CFID peripheral subsystem GPIO0/1/2/3/5 TIMER 0/1/2/3 SPI0/1/2 UART0/1 WDT Fig 4. LPC2926/2927/2929 overview of clock areas LPC2926_27_29 Product data sheet BA SE_ICLK0_CLK BASE_SYS_CLK BASE_ICLK1_CLK BASE_IVNSS_CLK branch clocks BASE_PCR_CLK BASE_MSCSS_CLK CGU0 All information provided in this document is subject to legal disclaimers. ...
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... Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK LPC2926_27_29 Product data sheet contains an overview of all the base blocks in the LPC2926/2927/2929 and their for more details of how to control the individual branch clocks. CGU0 base clock and branch clock overview Branch clock name CLK_SAFE CLK_SYS_CPU CLK_SYS_SYS ...
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... CGU1 base clock and branch clock overview Branch clock name CLK_OUT_CLK CLK_USB_CLK CLK_USB_I2C_CLK All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 …continued Parts of the device clocked by this branch clock APB side of the MSCSS Timer 0 in the MSCSS Timer 1 in the MSCSS ...
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... LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 time (see Section 9). During this init © NXP B.V. 2010. All rights reserved ...
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... Section 6.6.3. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 9. Section 6.7.2. © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Sector base address 0x2000 0000 0x2000 2000 0x2000 4000 0x2000 6000 0x2000 8000 0x2000 A000 0x2000 C000 ...
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... It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the flash controller. 6.9 External static memory controller The LPC2926/2927/2929 contains an external Static Memory Controller (SMC) which provides an interface for external (off-chip) memory devices. Key features are: • ...
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... Pin description The external static-memory controller module in the LPC2926/2927/2929 has the following pins, which are combined with other functions on the port pins of the LPC2926/2927/2929. Table 13. Symbol EXTBUS CSx EXTBUS BLSy EXTBUS WE EXTBUS OE EXTBUS A[23:0] A[23:0] EXTBUS D[31:0] D[31:0] 6 ...
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... A D WSTWEN WSTWEN = 3, WST2 = 7 to write enable (8 bit devices). Writing to external memory All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB WST1 002aae704 Figure 6. The relationship WST2 002aae705 © NXP B.V. 2010. All rights reserved. ...
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... A D WST1 WSTOEN WSTOEN = 2, WSTWEN = 4, WST1 = 6, WST2 = 4, IDCY = 5 Reading/writing external memory All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Figure 7. Extra wait states WST2 WSTWEN IDCY 002aae706 © NXP B.V. 2010. All rights reserved. ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC2926/2927/2929 can enter the Power-down mode and wake up on USB activity. • Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints. • ...
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... USB reset status USB transceiver interrupt Bus suspend status Section 6.7.2. The CGU1 provides two independent base clocks to All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 Connection USB Connector USB Connector USB Connector Control Control External OTG transceiver ...
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... System Control Unit (SCU) The system control unit contains system-related functions. The key feature is configuration of the I/O port-pins multiplexer. It defines the function of each I/O pin of the LPC2926/2927/2929. The I/O pin configuration should be consistent with peripheral function usage. The SCU has no external pins. 6.12.4 Event router The event router provides bus-controlled routing of input events to the vectored interrupt controller for use as interrupt or wake-up signals ...
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... NXP Semiconductors 6.12.4.1 Pin description The event router module in the LPC2926/2927/2929 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2926/2927/2929. Table 15 Table 15. Symbol EXTINT[0:7] CAN0 RXD CAN1 RXD I2C0_SCL I2C1_SCL LIN0 RXD LIN1 RXD ...
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... CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on. 6.13.3 Timer The LPC2926/2927/2929 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem ...
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... SubSystem. In the Modulation and Sampling SubSystem each timer also has its own individual clock source. See 6.13.3.1 Pin description The four timers in the peripheral subsystem of the LPC2926/2927/2929 have the pins described below. The two timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1. See description of these timers and their associated pins ...
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... The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx. 6.13.5 Serial Peripheral Interface (SPI) The LPC2926/2927/2929 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals. The key features are: • ...
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... Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB. 6.13.5.2 Pin description The SPI pins are combined with other functions on the port pins of the LPC2926/2927/2929, see y runs from 0 to 3). Table 18. Symbol SPIx SCSy ...
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... Pin description The five GPIO ports in the LPC2926/2927/2929 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2926/2927/2929. shows the GPIO pins. ...
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... Controller Area Network (CAN) is the definition of a high-performance communication protocol for serial data communication. The two CAN controllers in the LPC2926/2927/2929 provide a full implementation of the CAN protocol according to the CAN specification version 2.0B. The gateway concept is fully scalable with the number of CAN controllers, and always operates together with a separate powerful and flexible hardware acceptance filter ...
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... NXP Semiconductors 6.14.1.2 Pin description The two CAN controllers in the LPC2926/2927/2929 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2926/2927/2929. Table 20 Table 20. Symbol CANx TXD CANx RXD 6.14.2 LIN The LPC2926/2927/2929 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2 ...
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... Note that the pins are not I 6.15 Modulation and sampling control subsystem The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2926/2927/2929 includes four Pulse Width Modulators (PWMs), three 10-bit successive approximation Analog-to-Digital Converters (ADCs) and two timers. The key features of the MSCSS are: • ...
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... LPC2926_27_29 Product data sheet provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of 6.16.2. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB © NXP B.V. 2010. All rights reserved ...
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... PWM1 TRAP PWM1 CAP[2:0] PWM2 TRAP PWM2 CAP[2:0] PWM3 TRAP PWM3 CAP[2:0] All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB IDX0 PHA0 PHB0 ADC0 IN[7:0] ADC1 IN[7:0] ADC2 IN[7:0] ADC2 EXT START ...
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... NXP Semiconductors 6.15.2 Pin description The pins of the LPC2926/2927/2929 MSCSS associated with the three ADC modules are described in Section Section Section 6.15.3 Clock description The MSCSS is clocked from a number of different sources: • CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge • ...
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... ADC block diagram 6.15.4.2 Pin description The three ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2926/2927/2929. The VREFN and VREFP pins are common to all ADCs. LPC2926_27_29 Product data sheet Figure 9, shows the basic architecture of each ADC ...
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... DDA ADC3V3 2 2 Section All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB analog input for 5.0 V ADC0, channel 7 to channel 0. analog input for 3.3 V ADC1/2, channel 7 to channel 0. ADC external start-trigger input. ...
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... NXP Semiconductors 6.15.5 Pulse Width Modulator (PWM) The MSCSS in the LPC2926/2927/2929 includes four PWM modules with the following features. • Six pulse-width modulated output signals • Double edge features (rising and falling edges programmed individually) • Optional interrupt generation on match (each edge) • ...
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... A mechanism is included to synchronize the PWM period to other PWMs by providing a sync input and a sync output with programmable delay. Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Figure 8 LPC2926/2927/2929. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. LPC2926_27_29 Product data sheet APB DOMAIN ...
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... A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode). 6.15.5.4 Pin description Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2926/2927/2929. PWM0 to PWM3 pins. Table 24. Symbol ...
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... NXP Semiconductors 6.15.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2926/2927/2929. MSCSS timer 1 external pin. Table 25. Symbol MSCSS PAUSE 6.15.6.2 Clock description The timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx ( 1), see Section power management ...
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... If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off. 6.16 Power, Clock and Reset Control Subsystem (PCRSS) The Power, Clock and Reset Control Subsystem in the LPC2926/2927/2929 includes the Clock Generator Units (CGU0 and CGU1), a Reset Generator Unit (RGU) and a Power Management Unit (PMU) ...
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... FDIV[6:0] OUT7 OUT9 RGU RESET OUTPUT DELAY LOGIC INPUT DEGLITCH/ SYNC Section 6.7.2. CLK_SYS_PCRSS is derived from All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 PMU CGU1 OUT0 OUT1 OUT2 CLOCK GATES CLOCK ENABLE CONTROL PMU REGISTERS AHB_RST ...
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... Maximum frequency that guarantees stable operation of the LPC2926/2927/2929. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2926_27_29 Product data sheet CGU0 base clocks ...
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... FDIV6 CLOCK DETECTION AHB TO DTL BRIDGE Table 27 for all base clocks) Figure 12. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB OUT 0 OUT 1 OUT 2 OUT 3 OUT 11 002aae147 BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK ...
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... For every output generator generating the base clocks a LP_OSC EXTERNAL OSCILLATOR PLL Every secondary clock generator or output generator is Clocks that are inactive are automatically regarded as invalid, All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 FDIV0:6 clkout clkout120 clkout240 OUTPUT CONTROL clock outputs © ...
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... Figure . These clocks are either divided by 2 × the programmable post 2 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 14. The input clock is fed directly to the Table 36, Dynamic characteristics. © NXP B.V. 2010. All rights reserved ...
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... Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When Power-down mode is terminated by clearing the PD control-register bit the PLL resumes normal operation, and makes the LOCK signal high once it has regained lock on the input clock. 6.16.2.3 Pin description The CGU0 module in the LPC2926/2927/2929 has the pins listed in Table 28. Symbol XOUT_OSC XIN_OSC ...
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... PLL clkout240 BASE_ICLK1_CLK Fig 15. Block diagram of the CGU1 6.16.3.1 Pin description The CGU1 module in the LPC2926/2927/2929 has the pins listed in Table 29. Symbol CLK_OUT 6.16.4 Reset Generation Unit (RGU) The RGU controls all internal resets. The key features of the Reset Generation Unit (RGU) are: • ...
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... WARM_RST WARM_RST WARM_RST WARM_RST All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 Table 30. The first five resets listed in Parts of the device reset when activated LP_OSC; is source for RGU_RST RGU internal; is source for PCR_RST parts with COLD_RST as reset source below ...
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... Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2926/2927/2929. Output clocks branched from the same base clock are phase- and frequency-related. These branch clocks can be individually controlled by software programming ...
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... BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 Implemented switch on/off mechanism WAKE-UP AUTO ...
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... CLK_TMR3 CLK_ADC0 CLK_ADC1 CLK_ADC2 CLK_USB_I2C CLK_USB 6.17 Vectored Interrupt Controller (VIC) The LPC2926/2927/2929 contains a very flexible and powerful Vectored Interrupt Controller to interrupt the ARM processor on request. The key features are: • Level-active interrupt request with programmable polarity. • 56 interrupt request inputs. • ...
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... Software emulation of an interrupt-requesting device, including interrupts. 6.17.2 Clock description The VIC is clocked by CLK_SYS_VIC, see LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 6.7.2. © NXP B.V. 2010. All rights reserved ...
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... I/O port 2 pins 12 and 13; I/O port 3 pins 0 and 1. average value per input pin drive HIGH, output shorted to V SS(IO) drive LOW, output shorted to V DD(IO) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 Min Max [1] - 1.5 −0.5 +2.0 −0.5 +2.0 −0.5 +4.6 −0.5 +6.0 − ...
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... I(ADC) ⁄ performed on the input voltage before feeding into the ADC0 itself. The maximum input 3 . All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Min Max −2000 [9] +2000 −500 +500 − ...
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... I/O pins, RST, TRST, TDI, JTAGSEL, TMS, TCK all port pins, RST, TRST, TDI, JTAGSEL, TMS, TCK All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB = 3 5.5 V; DDA(ADC5V0) Min Typ Max 1.71 1 ...
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... V OH DD(IO) without 33 Ω external series resistor − 0 DD(IO) with 33 Ω external series resistor All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB = 3 5.5 V; DDA(ADC5V0) Min Typ Max - - 0.8 0 ...
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... V DDA(ADC3V3) DDA(ADC5V0) DDA(ADC3V3) . I(ADC) are the two external load capacitors. ext must be above V DD(CORE) trip(high) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB = 3 5.5 V; DDA(ADC5V0) Min Typ Max 26.7 - 57.2 5.0 - 5.5 ...
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... T ADC and the ideal transfer curve. See [8] See Figure 16. ADC IN[y] Fig 16. Suggested ADC interface - LPC2926/2927/2929 ADC1/2 IN[y] pin LPC2926_27_29 Product data sheet − ° ° +85 C unless otherwise specified ...
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... LSB (ideal (LSB ) IA ideal ). D ). All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB (1) 1018 1019 1020 1021 1022 1023 offset gain error error 1024 002aae703 © ...
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... Conditions: T amb but not configured to run. at different core voltages V DD(CORE) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 90 core frequency (MHz) 1.8 core voltage (V) (active mode) DD(CORE) ...
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... DD(CORE) 500 OL 400 300 200 100 0 1.0 2.0 3 3.3 V. DD(IO) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 35 60 temperature (°C) 85 °C 25 °C 0 °C −40 °C 4.0 5.0 I 002aae239 85 002aae689 6.0 (mA) OL © ...
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... Product data sheet 3.5 OH (V) 3.0 2.5 2.0 1.0 2 3.3 V. DD(IO) 80 I(pd −40 − 3 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 85 °C 25 °C 0 °C −40 °C 3.0 4.0 5 3.6 V DD(IO) 3 temperature (°C) 002aae690 6.0 I (mA) OH 002aae691 85 © ...
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... I(pu) −40 −60 −80 −100 −40 − All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB V = 2.7 V DD(IO) 3 temperature (°C) 002aae692 85 © NXP B.V. 2010. All rights reserved. ...
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... CCO; direct mode on CAN TXDC pin = 25 °C (final testing). Both pre-testing and final testing use correlated amb All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB [1] Min Typ Max ...
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... Product data sheet 520 510 500 490 480 −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 1.9 V 1 temperature (°C) 002aae373 85 © NXP B.V. 2010. All rights reserved. ...
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... Figure 26 must accept as EOP; see Figure 26 crossover point crossover point differential data to SE0/EOP skew n × PERIOD FDEOP All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Min Typ 8 1.3 - 160 - − ...
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... DDA(ADC3V3) Conditions °C (final testing). Both pre-testing and final testing use correlated amb All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB [1] [2] Min Typ 20 + 0.1 × ...
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... Figure °C (final testing). Both pre-testing and final testing use correlated amb t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB = 3 5.5 V; DDA(ADC5V0) Min Typ ⁄ 1 ...
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... V to 3.6 V; all voltages are measured with respect to ground. Parameter Conditions clock frequency endurance retention time powered All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB ; 3.6 V; DD(IO) Min Typ [1] 10000 ...
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... Both pre-testing and final testing use correlated amb All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Typ - - - −2.5 −2.5 − WSTOEN × T CLCL 0 + WSTOEN × ...
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... ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t CSLWEL t WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 t CSHOEH t h(D) 002aae687 t CSHBLSH t WELWEH 002aae688 © NXP B.V. 2010. All rights reserved ...
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... Duty cycle clock should be as close as possible 10. Application information 10.1 Operating frequency selection The LPC2926/2927/2929 is specified to operate at a maximum frequency of 125 MHz, maximum temperature of 85 °C, and maximum core voltage of 1.89 V. Figure 31 LPC2926/2927/2929 by controlling the temperature and the core voltage accordingly. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 65 temperature (°C) 1.85 core voltage (V) 002aae194 85 002aae193 1.95 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2926/2927/2929 USB interface on a self-powered device LPC29xx Fig 33. LPC2926/2927/2929 USB interface on a bus-powered device LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ USB_VBUS Ω ...
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... NXP Semiconductors USB_RST LPC29xx USB_SCL USB_SDA USB_INT USB_D+ USB_D− Fig 34. LPC2926/2927/2929 USB OTG port configuration USB_UP_LED USB_CONNECT LPC29xx USB_D+ USB_D− USB_VBUS Fig 35. LPC2926/2927/2929 USB device port configuration LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) R1 ...
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... DATA VALID SDIn MSB IN SDOn MSB OUT SDIn MSB IN SDOn MSB OUT All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 DATA VALID LSB OUT DATA VALID LSB IN LSB OUT LSB IN DATA VALID LSB IN DATA VALID LSB OUT ...
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... Product data sheet ARM9 microcontroller with CAN, LIN, and USB which attenuates the input voltage by a factor C g LPC29xx XIN_OSC C i 100 pF All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 /( 002aae730 and C , and C x1 ...
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... 0.20 20.1 20.1 22.15 22.15 0.5 0.09 19.9 19.9 21.85 21.85 REFERENCES JEDEC JEITA MS-026 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB detail 0.75 1.4 1 0.2 0.08 0.08 ...
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... Solder bath specifications, including temperature and impurities LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 © NXP B.V. 2010. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 40. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 Figure 40) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved. ...
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... SCU Function Select Port x, y (use without the P if there are Test Access Port Transistor-Transistor Logic Universal Asynchronous Receiver Transmitter All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 © NXP B.V. 2010. All rights reserved ...
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... LPC2927_29 v.1 20090115 LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Data sheet status Product data sheet • Added LPC2926 device. Product data sheet • Section 1: Target market “medical” removed. • Document template updated. • USB logo added. ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 © NXP B.V. 2010. All rights reserved ...
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... Synchronizing the PWM counters . . . . . . . . . 45 6.15.5.3 Master and slave mode . . . . . . . . . . . . . . . . . 46 6.15.5.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 46 6.15.5.5 Clock description . . . . . . . . . . . . . . . . . . . . . . 46 6.15.6 Timers in the MSCSS 6.15.6.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 47 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 2 C-bus serial I/O controllers . . . . . . . . . . . . . 37 © NXP B.V. 2010. All rights reserved. continued >> ...
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... For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2926/2927/2929 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 88 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 91 Legal information . . . . . . . . . . . . . . . . . . . . . . 92 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 92 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Contact information . . . . . . . . . . . . . . . . . . . . 93 Contents Date of release: 28 September 2010 Document identifier: LPC2926_27_29 All rights reserved. ...