ak5366vr AKM Semiconductor, Inc., ak5366vr Datasheet - Page 34

• Manufacturer Part Number: ak5366vr
• Description: 24-bit 48khz Adc With Selector/pga/alc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
T Register Definitions
PWN: Power down control
MCKAC: Master Clock input Mode Select
MCKPD: MCLK Input Buffer Control
SEL2-0:
SMUTE: Soft Mute control
CKS1-0: Master clock frequency select (see Table 2)
DIF:
MS0526-E-00
Addr
Addr
Addr
00H
01H
02H
Audio interface format (see Table 4)
Register Name
Power Down & Reset Control
Register Name
Input Selector Control
Register Name
Clock & Format Control
0 : Power down. All registers are not initialized.
1 : Normal Operation (Default)
0 : CMOS input (Default)
1 : AC coupling input
0 : Enable (Default)
1 : Disable
Input selector (see Table 6)
0 : Normal Operation (Default)
1 : SDTO outputs soft-muted.
Initial values are “00”.
Initial values are “0” (24bit, MSB first).
Default
Default
Default
R/W
R/W
R/W
“0” powers down all sections and then both IPGA and ADC do not operate. The contents of all register
are not initialized and enabled to write to the registers.
When MCLK and LRCK are changed, it is not necessary to reset by the PDN pin or PWN bit because the
AK5366VR builds in reset-free circuit. However, it can be reduced the noise by reset.
When MCLK input with AC coupling is stopped, MCKPD bit should be set to “1”.
Initial values are “000”.
RD
RD
D7
D7
RD
D7
0
0
0
0
0
0
RD
RD
RD
D6
D6
D6
0
0
0
0
0
0
- 34 -
RD
RD
RD
D5
D5
D5
0
0
0
0
0
0
RD
RD
RD
D4
D4
D4
0
0
0
0
0
0
R/W
DIF
RD
RD
D3
D3
D3
0
0
0
0
0
MCKPD
CKS1
SEL2
R/W
R/W
R/W
D2
D2
D2
0
0
0
MCKAC
CKS0
SEL1
R/W
R/W
R/W
D1
D1
D1
0
0
0
[AK5366VR ]
SMUTE
2006/07
SEL0
PWN
R/W
R/W
R/W
D0
D0
D0
0
0
1