ak4384 AKM Semiconductor, Inc., ak4384 Datasheet - Page 9

• Manufacturer Part Number: ak4384
• Description: 106db 192khz 24-bit 2ch ?? Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The external clocks, which are required to operate the AK4384, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4384 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes
the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
In parallel mode, the sampling speed can be set by ACKS pin. The internal DFS0 andDFS1 bits are fixed to “0”.
Therefore, when ACKS pin is “L”, the AK4384 operates in Normal Speed Mode. The AK4384 operates in Auto Setting
Mode at ACKS = “H”. In parallel mode, the AK4384 does not support 128fs and 192fs of Double Speed Mode.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4384 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4384 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4384 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4384 should be in the power-down
mode (PDN= “L”). After exiting reset at power-up etc., the AK4384 is in the power-down mode until MCLK and LRCK
are input.
MS0176-E-01
System Clock
32.0kHz
44.1kHz
48.0kHz
LRCK
fs
88.2kHz
96.0kHz
LRCK
fs
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz
256fs
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
DFS1
0
0
1
128fs
Table 1. Sampling Speed (Manual Setting Mode)
DFS0
384fs
0
1
0
OPERATION OVERVIEW
192fs
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
MCLK
MCLK
512fs
- 9 -
256fs
Sampling Rate (fs)
768fs
120kHz~192kHz
60kHz~96kHz
384fs
8kHz~48kHz
36.8640MHz
1152fs
N/A
N/A
5.6448MHz
6.1440MHz
BICK
64fs
Default
2.0480MHz
2.8224MHz
3.0720MHz
BICK
64fs
[AK4384]
2006/01