xr16m2750 Exar Corporation, xr16m2750 Datasheet - Page 8

• Manufacturer Part Number: xr16m2750
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16M2750
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M2750 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels
share the same data bus for host operations. The data bus interconnections are shown in
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The XR16M2750 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide
0x0A for the XR16M2750 and reading the content of DLL will provide the revision of the part; for example, a
reading of 0x01 means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A LOW signal on the chip select pins, CSA# or CSB#,
allows the user to select UART channel A or B to configure, send transmit data and/or unload receive data to/
from the UART. Selecting both UARTs can be useful during power up initialization to write to the same internal
F
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.4
IGURE
3. XR16M2750 D
CPU Interface
Device Reset
Device Identification and Revision
Channel A and B Selection
UART_RESET
Table
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
RXRDYA#
RXRDYB#
TXRDYA#
TXRDYB#
IOW#
IOR#
16). An active high pulse of longer than 40 ns duration will be required to activate the reset
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
ATA
B
US
I
NTERCONNECTIONS
8
IOW#
CSA#
CSB#
IOR#
INTA
INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
Channel A
Channel B
UART
UART
DTRA#
DSRA#
RTSA#
CTSA#
DTRB#
DSRB#
OP2A#
RTSB#
CTSB#
OP2B#
CDA#
CDB#
GND
RIA#
RIB#
VCC
TXA
RXA
TXB
RXB
VCC
Serial Interface of
Serial Interface of
RS-232, RS-485
RS-232, RS-485
Figure
2750int
3.
REV. 1.0.0