xr68c92 Exar Corporation, xr68c92 Datasheet
xr68c92
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xr68c92 Summary of contents
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... The baud rate generator and counter/timer can operate directly from a crystal or from external clock input. The XR68C92/192 provides a power-down mode in which the oscillator is stopped but the register contents are retained. The XR68C92/192 is fabricated in an advanced CMOS process to achieve low power and high speed requirements. ...
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... XTAL1 OP1 7 31 RXA OP3 8 30 TXA OP5 9 29 OP0 OP7 10 28 OP2 N.C. 11 OP4 27 26 OP6 -INT 2 44 Pin LQFP Package XR68C92 28 XR68C192 -CS -RESET XTAL2 XTAL1 RXA TXA OP0 OP2 OP4 OP6 N.C. ...
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... Block Diagram D0-D7 R/-W -DTACK -IACK -RESET A0-A3 -CS -INT XTAL1 XTAL2 Rev. 1.33 XR68C92/192 Channel A Transmit Transmit FIFO Shift Registers Register Flow Control Logic Receive Receive FIFO Shift Registers Register Watch Flow Dog Control Timer Logic Channel B Transmit Transmit FIFO Shift Registers Register Flow Control ...
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... I Read/Write strobe. When -CS is asserted, a high on this pin transfers the contents of the XR68C92/192 data bus to the CPU, and a low on this pin will transfer the contents of the CPU data bus to the addressed register Interrupt output (open drain, active low) This pin goes low upon occurrence of one or more of eight maskable interrupt conditions (when enabled by the interrupt mask register) ...
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... Crystal input 2 or buffered clock output. See XTAL1. 29,5 I Serial data input. The serial information (data) received from serial port to XR68C92/192 receive input circuit. A mark (high) is logic one and a space (low) is logic zero.This input must be held at logic one when idle and during power down. 28,6 O Serial data output ...
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... XR68C92/192 SYMBOL DESCRIPTION (* 44 pin LQFP) Symbol Pin 44 40 OP3 15 13 OP4 30 27 OP5 16 14 OP6 29 26 OP7 17 15 GND 22 20 16,17 VCC 44 40 38,39 N.C. 1,12 - 11,23 23,34 Rev. 1.33 Signal Pin Description 44* type following functions can be selected for this output pin by programming the Output Port Confiuration Register bits 1,0; ...
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... The programmable 16-bit counter/timer (C/T) can pro- duce a 16X clock for other baud rates by counting down its programmed clock source. Users can program the 16 bit C/T within the XR68C92/192 to use one of several clock sources as its input. The output of the available to the internal clock selectors and can also be programmed to appear at output OP3 ...
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... It is controlled by the internal control logic to allow read and write data transfer operations to occur between the controlling CPU and XR68C92/192 by way of the eight parallel data lines (D0 through D7). MULTI-PURPOSE INPUTS (IP0 - IP5) The states of the seven multi-purpose inputs (IP0 through IP5) can be read from the internal register IPR (address 0x0D) ...
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... Figure 1 external CMOS-level clock is used, the pin XTAL2 must be left open. RESET The XR68C92/192 can be reset by asserting the -RESET signal or by programming the appropriate internal registers. A hardware reset (assertion of -RESET) clears the following registers: • ...
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... In this process, the least significant bit is received first. The receiver buffer is composed of the FIFO (8/16 Rev. 1.33 locations in XR68C92/192 respectively) and a receive shift register connected to the receiver serial-data input. Data is assembled in the shift register and loaded into the bottom most empty FIFO location. If the character length is less than eight bits, the most significant unused bits are set to zero ...
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... LOOPBACK MODES Besides the normal operation mode in which the re- ceiver and transmitter operate independently, each XR68C92/192 channel can be configured to operate in various looping modes (see MR2A, MR2B bits 7:6) that are useful for local and remote system diagnostic functions. AUTOMATIC ECHO MODE In this mode, the channel automatically retransmits the received data on a bit-by-bit basis ...
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... Extra Storage For The A/D Tag: The unique feature of XR68C92/192 is that the the user need not wait at all in order to change the A/D tag from address to data (whereas in the case of SC26C92, a wait of at least 2 bit-times is required before changing the A/D tag). This allows the user to possibly load the entire polling packet data to the TX FIFO ...
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... In the timer mode, the C/T runs continuously once the start command is issued (by reading the start C/T TERMINAL PRELOAD TERMINAL PRELOAD COUNT VALUE COUNT VALUE PRELOAD TERMINAL PRELOAD TERMINAL VALUE COUNT VALUE COUNT TERMINAL COUNT 13 XR68C92/192 TERMINAL PRELOAD COUNT VALUE PRELOAD TERMINAL VALUE COUNT ...
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... XR68C92/192 command register) and the CPU cannot stop it. When the stop command is issued (by reading the stop C/T command register), the CPU only resets the C/T inter- rupt. This mode allows the C used as a programmable clock source for channels A and B (see CSRA, CSRB register), and/or a periodic interrupt generator ...
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... Start C/T Command (STCR Stop C/T Command (SPCR) Rev. 1.33 XR68C92/192 WRITE Operation Mode Register A (MR0A, MR1A, MR2A) Clock-Select Register A (CSRA) Command Register A (CRA) Transmitter Buffer A (TXA) Auxiliary Control Register (ACR) Interrupt Mask Register (IMR) C/T Preload value Upper Register (CTPU) C/T Preload value Lower Register (CTPL) ...
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... XR68C92/192 Register BIT-7 [Default MRA0[00] Watch dog timer MRB0[00] Watch dog timer MRA1[00 MRB1[00] RTS control MRA2[00] Loopback Loopback MRB2[00] mode select SRA[00] Received ...
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... FIFO bytes in FIFO bytes in FIFO Rev. 1.33 XR68C92/192 MR0A, MR0B Bit-7: Receive time-out (watch dog timer Disabled (default Enabled See description under 'Watchdog Timer'. MODE REGISTER 1 (MR1A, MR1B) MR1A, MR1B are accessed after reset or by command applied via CRA, CRB register (upper nibble = 0x1). ...
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... XR68C92/192 two reset MR pointer command (see Command Register) to reset the pointer to MR0 or MR1. MR2A, MR2B Bits 3-0: Stop bit length. 0000 = 0.563 (default) 1000 = 1.563 0001 = 0.625 1001 = 1.625 0010 = 0.688 1010 = 1.688 0011 = 0.750 1011 = 1.750 0100 = 0.813 1100 = 1.813 0101 = 0.875 1101 = 1 ...
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... Reset Channel's Break-Change Interrupt. Clears channel A/B break detect change bit in the interrupt status register (ISR bit-2 for channel A and ISR bit-6 for channel B). 19 XR68C92/192 MR0A Bit-0=0 Bit-2=1 (extended table 2) SET-1 SET-2 ACR ...
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... CPU or flushed by a reset receiver command. TRANSMIT BUFFER (TXA, TXB) The transmit buffer consists of a 8-characters deep FIFO in XR68C92 and 16-characters deep FIFO in XR68C192. Once loaded in the FIFO, the characters are transferred to the transmit shift register one at a time and transmitted unless the transmitter is disabled. ...
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... Reading the ISR has no effect on any interrupt source. Each active interrupt source must be cleared in a source-specific fashion to clear the ISR. All interrupt sources are cleared when the XR68C92/192 is ISR Bit-0: Transmit ready A. This bit is set when channel A's transmit buffer (FIFO) is filled below the programmed transmit trigger level (see MR0A bits 5-4) ...
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... XR68C92/192 INTERRUPT MASK REGISTER (IMR) This register selects which bits in the interrupt status register can cause an interrupt output bit in the interrupt status register is a “1” and the corresponding bit in this register is also a “1”, the -INT output will be asserted. If the corresponding bit in this register is a zero, the state of the bit in the interrupt status register has no effect on the -INT output ...
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... OP0. SOPR Bit 0- change (same state Assert the corresponding output (Set it low). Rev. 1.33 XR68C92/192 RESET OUTPUT PORT REGISTER (ROPR) - Write Only Each output port bit can be changed to high state by writing a “1” to each individual bit. ROPR Bit 0- change (same state) ...
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... XR68C92/192 PROGRAMMING EXAMPLES The following examples show how to initialize the XR68C92/192 for various operating conditions: A) The first example will initialize channel XR68C92 device for regular RX/TX. The operating parameters will be 9600 baud, 8 word length, no parity and 1 stop bit. Operation Register Value ...
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... ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS FOR XR68C92 AND XR68C192 T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter V Clock input low level ILCK ...
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... XR68C92/192 AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T T Clock pulse duration 1w Oscillator/Clock frequency 3w T Address Valid to -CS Low AS T -CS High to Address Invalid AH T R/-W Setup Time to -CS Low RWS ...
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... T AS A4-A1 R/-W -CS T D7-D0 -DACK T AS A4-A1 R/-W -CS D7-D0 -DACK Figure 3: Bus Timing (Read/Write cycle) Rev. 1. RWS T CSL DD Valid Data T AKT T AKL Read Cycle Timing RWS T CSL AKT T AKL Write Cycle Timing 27 XR68C92/192 RWH T CSH AKH RWH T CSH AKH ...
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... XR68C92/192 IP6-IP0 T9s -CS -CS OP7-OP0 ExCLK -INT -IACK D7-D0 -DACK Rev. 1.33 T9h Figure 4: Input Port Timing T10d Old Data Figure 5: Output Port Timing T1w T2w T3w Figure 6: External clock Timing Interrupt Vector T T AKL AKH T AKT Figure 7: Interrupt Timing 28 XR92-IP ...
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... Rev. 1. D10 Status Data (D2) D11 Will be lost due to overrun Figure 8: Receive Timing Break D2 D3 Figure 9: Transmit Timing 29 XR68C92/192 D11 D12 D13 D12, D13 Will be lost due to RX disable Status Data Status Data (D3) (D10) Reset by command XR92- XR692-TX ...
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... XR68C92/192 P ACKAGE OUTLINE DRAW ING Seat ing Plane L B Note ontrol dimens ion is the inc h c olumn SY MBOL α Rev. 1. EAD PLASTIC DUAL-IN-LINE (PDIP α ...
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... BSC 1.27BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 31 XR68C92/192 C Seat ing Plane ° 4.57 3.05 ------ 0.53 0.81 0.32 17.65 16.66 16.00 1.42 1.22 1.14 ...
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... XR68C92/192 PACKAGE OUTLINE DRAWING A Seating Plane A Note: The control dimension is the inch column SYMBOL Rev. 1.33 44 LEAD LOW-PROFILE QUAD FLAT PACK (LQFP INCHES MIN MAX MIN A 0.055 0.063 1.40 A 0.002 0.006 0. 0.053 0.057 1 ...
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... EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet August 2005 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 1.33 XR68C92/192 CHANGES NOTICE 33 DATE August 2003 ...