sc16c850iet NXP Semiconductors, sc16c850iet Datasheet - Page 11

• Manufacturer Part Number: sc16c850iet
• Description: Sc16c850 2.5 V To 3.3 V Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C850_1
Product data sheet
6.4.1 32-byte FIFO mode
6.4.2 128-byte FIFO mode
6.4 FIFO operation
Table 5.
[1]
[2]
[3]
[4]
[5]
[6]
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
‘first extra feature register set’ are empty (0x00) the transmit and receive trigger levels are
set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward
compatible to the SC16C650B (see
transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).
It should be noted that the user can set the transmit trigger levels by writing to the FCR,
but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section
includes a time-out function to ensure data is delivered to the external CPU (see
Section
Table 6.
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contains any value other than 0x00, the transmit and receive trigger levels are
set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the
transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128
with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive
trigger levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
A2
Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)
0
1
1
1
FCR[7:6]
00
01
10
11
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Second Special registers are accessible only when EFCR[0] = 1.
Enhanced Feature Registers are only accessible when LCR = 0xBF.
First Extra Feature Registers are only accessible when EFCR[2:1] = 01b.
Second Extra Feature Registers are only accessible when EFCR[2:1] = 10b.
A1
1
0
1
1
6.8). Please refer to
Internal registers decoding
Interrupt trigger level and flow control mechanism
A0
0
0
0
1
FCR[5:4]
00
01
10
11
Read mode
Clock Prescaler
RS-485 turn-around Timer
Additional Feature Control Register 2
Additional Feature Control Register 1
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 01 — 10 January 2008
INT pin activation
RX
8
16
24
28
Table 11
TX
16
8
24
30
Table
…continued
and
6), and the FIFO sizes are 32 entries. The
Table 12
Negate RTS or
send Xoff
8
16
24
28
for the setting of FCR[7:4].
Write mode
Clock Prescaler
RS-485 turn-around Timer
Additional Feature Control Register 2
Additional Feature Control Register 1
SC16C850
Assert RTS or
send Xon
0
7
15
23
© NXP B.V. 2008. All rights reserved.
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