pt7a7521w Pericom Technology Inc, pt7a7521w Datasheet - Page 8

• Manufacturer Part Number: pt7a7521w
• Description: ?p Supervisor Circuits
• Manufacturer: Pericom Technology Inc

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Functional Description
The PT75xx family can assert reset output during power-up,
power-down and brownout conditions for µP system, detect
power failure or low-battery conditions with a 1.25V threshold
detector and have watchdog functions. Refer to Function Table
of PT7A75xx Family for their individual features. The typical
application see Figure 4.
Reset Output
The supervisory circuits can assert reset for a microprocessor
during power-up, power-down and brownout to prevent code
execution errors.
On power-up, once V
guaranteed logic low of 0.4V or less. As V
low. When V
releases RESET after about 200ms. RESET pulses low whenever
V
brownout occurs in the middle of a previously initiated reset
pulse, the pulse continues for at least another 140ms.
On power-down, once V
stays low and is guaranteed to be 0.4V or less until Vcc drops
below 1V.
The PT7A752x and PT7A753x active-high RESET output is
simply the complement of the RESET output, and is guaranteed
to be valid with V
80C51, require an active-high reset pulse.
PT0082L(03/06)
Typical Application Circuit
CC
drops below the reset threshold (brownout condition). If
CC
rises above the reset threshold, an internal timer
CC
down to 1.2V. Some µPs, such as Intel’s
CC
CC
falls below the reset threshold, RESET
reaches about 1.2V, RESET is a
IN
DC Linear
Regulator
CC
rises, RESET stays
OUT
MR
Vcc
PFI
µ µ P
Circuit
Supervisory
8
Watchdog Timer
The watchdog circuit monitors the µP activity. If the µP does
not toggle the watchdog input (WDI) within 1.6sec and WDI is
not in high impedance, WDO goes low. As long as RESET is
asserted or the WDI input is in high impedance, the watchdog
timer will stay cleared and will not count. As soon as reset is
released and WDI is driven high or low, the timer will start
counting. Pulses as short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable interrupt
input (NMI) of a µP. When V
WDO will go low whether or not the watchdog timer has timed
out yet. Normally this would trigger an NMI interrupt, but RESET
goes low simultaneously, and thus overrides the NMI interrupt.
If WDI is left unconnected, WDO can be used as a low-line
output. Since floating WDI disables the internal timer, WDO
goes low only when V
functioning as a low-line output.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a
push-button switch. The switch is effectively debounced by
the 140ms minimum reset pulse width. MR is TTL/CMOS logic
compatible, so it can be driven by any logic reset output.
Power-Fail Comparator
The power-fail comparator will send out a Low signal once
detects a voltage lowered than 1.25V. It can be used for various
purposes because its output and non-inverting input are not
internally connected. The inverting input is internally connected
to a 1.25V reference.
PT7A7511-7515/7521-7525/7531-7535
RESET
WDO
WDI
PFO
CC
Vcc
falls below the reset threshold, thus
RESET
I/O Line
NMI
Interrupt
µ µ µ µ µ P Supervisor Circuits
CC
drops below the reset threshold,
µ µ P
Data Sheet
Ver:4