wm8753lgefl-v Wolfson Microelectronics plc, wm8753lgefl-v Datasheet
wm8753lgefl-v
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... PCM CODEC operation • 7x7x0.9mm QFN package, 5x5x0.9mm BGA package APPLICATIONS • MP3 Player / Recorder mobile phone • Bluetooth stereo headset at http://www.wolfsonmicro.com/enews/ WM8753L 2 S type link Production Data, September 2008, Rev 4.0 Copyright ©2008 Wolfson Microelectronics plc ...
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Production Data DESCRIPTION .......................................................................................................1 FEATURES ............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION - QFN................................................................................4 PIN CONFIGURATION - BGA ...............................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 SIMULATED THERMAL PROPERTIES......................................................................... 6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ...
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WM8753L VOICE FILTER RESPONSES..............................................................................84 VOICE DAC FILTER RESPONSES ............................................................................. 84 VOICE ADC FILTER RESPONSES ............................................................................. 84 DE-EMPHASIS FILTER RESPONSES ................................................................85 HIGHPASS FILTER..............................................................................................86 APPLICATIONS INFORMATION .........................................................................88 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 88 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS ........................................ 89 PACKAGE ...
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... Production Data PIN CONFIGURATION - QFN (TOP VIEW) ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8753LGEFL/V -25°C to +85°C WM8753LGEFL/RV -25°C to +85°C WM8753LGEB/V -25°C to +85°C WM8753LGEB/RV -25°C to +85°C Note: QFN Reel quantity = 2,200 BGA Reel quantity = 3,500 w PIN CONFIGURATION - BGA ...
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WM8753L PIN DESCRIPTION BGA QFN NAME J2 1 VXDOUT H3 2 VXCLK J3 3 VXFS H4 4 LRC J4 5 BCLK J5 6 ADCDAT H5 7 DACDAT J6 8 MCLK H6 9 DBVDD J7 10 DCVDD H7 11 DGND J8 ...
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Production Data 2. Unused BGA pins F8, C8, G2, A7 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits ...
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WM8753L ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.5V, AVDD = HPVDD = DBVDD = SPKRVDD = PLLVDD = 3.3V, T data unless otherwise stated. PARAMETER Analogue Inputs (LINE1, LINE2, RXP, RXN) Full-scale Input Signal Level V (0dB) – note this ...
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Production Data Test Conditions DCVDD = 1.5V, AVDD = HPVDD = DBVDD = SPKRVDD = PLLVDD = 3.3V, T data unless otherwise stated. PARAMETER Voice Digital to Analogue Converter (DAC) to Lineout (LOUT1/2, ROUT1/2, MONO1, MONO2,OUT3 with 10kΩ / 50pF ...
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WM8753L Test Conditions DCVDD = 1.5V, AVDD = HPVDD = DBVDD = SPKRVDD = PLLVDD = 3.3V, T data unless otherwise stated. PARAMETER Microphone Bias Bias Voltage (MBVSEL=0) Bias Voltage (MBVSEL=1) Bias Current Source Output Noise Voltage Digital Input / ...
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Production Data OUTPUT PGA’S LINEARITY 10.000 0.000 Output PGA Gains -10.000 -20.000 -30.000 -40.000 -50.000 -60.000 -70.000 40 50 2.000 1.750 Output PGA Gain Step Size 1.500 1.250 1.000 0.750 0.500 0.250 0.000 ...
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WM8753L POWER CONSUMPTION The power consumption of the WM8753L depends on the following factors. Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings. Operating mode: Power consumption is lower in mono modes ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2=0, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, T Slave Mode ...
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WM8753L Test Conditions DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MODE/GPIO3 ...
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Production Data AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, ...
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WM8753L CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN SDOUT Note: Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = ...
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Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = ...
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WM8753L INTERNAL POWER ON RESET CIRCUIT AVDD Figure 6 Internal Power on Reset Circuit Schematic The WM8750 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state after ...
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Production Data DEVICE DESCRIPTION INTRODUCTION The WM8753L is a low power audio CODEC combining a high quality stereo audio DAC with a high quality stereo ADC and mono DAC. The stereo ADC may be configured for operation as a mono ...
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WM8753L OUTPUT MIXERS Flexible mixing is provided on the outputs of the device; a stereo mixer is provided for the stereo headphone or line outputs, and an additional mono mixer for the mono output to the transmit side of the ...
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Production Data POWER CONTROL The design of the WM8753L has given much attention to power consumption without compromising performance. It operates at very low voltages, and includes the ability to power off any unused parts of the circuitry under software ...
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WM8753L RXN and RXP are inputs to a mixer controlled by the RXMSEL register bits. By default this is a differential input (RXP-RXN). The RX mixer can also be configured as a stereo to mono mix input (RXP+RXN). Alternatively RXP ...
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Production Data REGISTER ADDRESS R47 (2Fh) Input Control (1) Table 4 Input and Bypass Mux Control REGISTER ADDRESS R48 (30h) Input Control (2) Table 5 ALC Mix and Mic Mux Input Select w BIT LABEL DEFAULT LMSEL[1:0] 00 [4:3] 2 ...
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WM8753L REGISTER ADDRESS R32 (20h) Record Mix (1) R33 (21h) Record Mix (2) Table 6 Record Mixer Input Select and Gain Control MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can ...
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Production Data REGISTER ADDRESS R2 (02h) Additional Control (1) Table 8 ADC Data Output Configuration MICROPHONE INPUTS Figure 8 Internal Microphone Input Circuit There are two microphone pre-amplifiers which can be configured in a variety of ways to accommodate up ...
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WM8753L REGISTER ADDRESS R47 (2Fh) Mic Input Boost Table 10 MIC Preamp Gain Control The suggested configuration for the external microphone circuit is shown in Figure 9. Figure 9 Suggested External Microphone Input Configuration DIFFERENTIAL OPERATION It is possible to ...
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Production Data REGISTER ADDRESS R2 (02h) ADC control Table 11 ADC Polarity Control SINGLE ENDED OPERATION It is possible to connect up to three microphones single endedly. MIC1 input , microphone2 to the MIC2 input, microphone3 to the MIC2N input ...
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WM8753L VMID Figure 10 Microphone Bias Schematic MICBIAS CURRENT DETECT The WM8753L includes a microphone bias current detect circuit which allows the user to set thresholds for the microphone bias current, above which an interrupt will be triggered. There are ...
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Production Data PGA CONTROL The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically adjustable from –17.25dB to +30dB in 0.75dB steps. Each PGA can be controlled either by the user or by ...
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WM8753L ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8753L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input ...
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Production Data REGISTER ADDRESS R2 (02h) ADC Control Table 18 ADC Signal Path Control DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in 0.5dB steps. The ...
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WM8753L REGISTER ADDRESS R16(10h) Left ADC Digital Volume R17 (11h) Right Digital Volume Table 19 ADC Digital Volume Control AUTOMATIC LEVEL CONTROL (ALC) The WM8753L has an automatic level control that aims to keep a constant recording volume irrespective of ...
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Production Data The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register bits. An upper limit for the PGA ...
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WM8753L REGISTER ADDRESS R12 (0Ch) ALC Control 1 R13 (0Dh) ALC Control 2 R14 (0Eh) ALC Control 3 Table 21 ALC Control w BIT LABEL DEFAULT 8:7 ALCSEL 00 ALC function select [1:0] (OFF ALC off (PGA gain ...
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Production Data PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ...
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WM8753L REGISTER ADDRESS R19 (13h) 3D enhance Table 23 3D Stereo Enhancement Function When 3D enhancement is enabled (and/or the tone control for playback) it may be necessary to attenuate the signal by 6dB to avoid limiting. This is a ...
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Production Data OUTPUT SIGNAL PATH The WM8753L output signal paths consist of digital filters, a stereo Hi-Fi DAC, Voice DAC, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8753L is in ‘playback only’ or ...
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WM8753L REGISTER ADDRESS R8 (08h) Left Digital Volume R9 (09h) Right Channel Digital Volume Table 25 Digital Volume Control GRAPHIC EQUALISER The WM8753L has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data ...
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Production Data REGISTER ADDRESS R10 (0Ah) Bass Control R11 (0Bh) Treble Control Table 27 Graphic Equaliser HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC) After passing through the graphic equaliser filters, digital ‘de-emphasis’ can be applied to the audio data if necessary ...
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WM8753L REGISTER ADDRESS R1 (01h) DAC Control Table 28 HiFi DAC Control The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert ...
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Production Data OUTPUT MIXERS The WM8753L provides the option to mix the Hi-FI DAC output signals and Voice DAC output signal with analogue line-in signals from the bypass and sidetone paths. The level of the mixed-in signals can be controlled ...
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WM8753L REGISTER ADDRESS R34 (22h) Left Mixer Control (1) R35 (23h) Left Mixer Control (2) Table 32 Left Output Mixer Control REGISTER ADDRESS R36 (24h) Right Mixer Control (1) R37 (25h) Right Mixer Control (2) Table 33 Right Output Mixer ...
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Production Data REGISTER ADDRESS R38 (26h) Mono Mixer Control (1) R39 (27h) Mono Mixer Control (2) Table 34 Mono Output Mixer Control ANALOGUE OUTPUTS LOUT1/ROUT1 OUTPUTS The LOUT1 and ROUT1 pins can drive a 16Ω or 32Ω headphone or a ...
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WM8753L REGISTER ADDRESS R40 (28h) LOUT1 Volume R41 (29h) ROUT1 Volume Table 35 LOUT1/ROUT1 Volume Control LOUT2/ROUT2 OUTPUTS The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled and can also drive ...
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Production Data MONO1 OUTPUT The MONO1 pin can drive a mono line output. The signal volume on MONO1 can be adjusted under software control by writing to MONO1VOL. REGISTER ADDRESS R44 (2Ch) MONOOUT Volume Table 37 MONO1 Volume Control MONO2 ...
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WM8753L OUT4 OUTPUT The OUT4 output can be used to output a buffered Vmid for driving a mono or stereo headset in capless mode, output the signal from the record mixer or drive out an inverted LOUT2 signal. The output ...
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Production Data Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and L/ROUT1, L/ROUT2 and MONO1 can be ...
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WM8753L REGISTER ADDRESS R27 (1Bh) GPIO Control (1) Table 46 GPIO4 Control THERMAL SHUTDOWN The speaker and headphone outputs can drive very large currents. To protect the WM8753L from overheating a thermal shutdown circuit is included. If the device temperature ...
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Production Data It is recommended to connect the DC coupled headphone outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a ...
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WM8753L Figure 16 Interrupt Control Flowchart w HOST The interupt controller in the WM8753 is level sensitive, ensuring that interupts are always Write R27/R28 to detected even without a clock. configure GPIO INT pin This flowchart illustrates headphone detection, but ...
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Production Data REGISTER ADDRESS R25 (19h) Interrupt Polarity R26 (1Ah) Interrupt Mask R27 (1Bh) GPIO Control (1) Table 48 Interrupt Control w BIT LABEL DEFAULT 7 TSDIPOL 0 Controls polarity of thermal shutdown interrupts Interrupt when thermal shutdown ...
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WM8753L GENERAL PURPOSE INPUT/OUTPUT The WM8753L has four dual purpose input/output pins. • • • selection input. • • select input. Pin 44 (MODE/GPIO3) is sampled on powerup to determine the control interface mode (2-wire or 3- wire) of the ...
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Production Data REGISTER ADDRESS R27 (1Bh) GPIO Control (1) R28 (1Ch) GPIO Control (2) Table 49 GPIO Control Note: GPIO5 must not be used in 3-wire interface mode. GPIO5 pin is shared with 3-wire interface CSB. Enabling GPIO5 as an ...
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WM8753L DIGITAL AUDIO INTERFACES The WM8753L has two audio interfaces – a hi-fi audio interface and a voice audio interface. The hi-fi audio interface is used for the input of data to the hi-fi DAC and may also be used ...
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Production Data AUDIO DATA FORMATS – AUDIO INTERFACE AND VOICE INTERFACE In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted ...
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WM8753L LRC / VXFS BCLK / VXCLK DACDAT / ADCDAT / VXDIN / VXDOUT Figure 19 Right Justified Audio Interface (assuming n-bit word length mode, the MSB is available on the second rising edge of BCLK ...
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Production Data Figure 22 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w WM8753L PD, Rev 4.0, September 2008 56 ...
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WM8753L The Voice Interface may be configured for Mono mode, where only one channel of data is input or output. In this mode the interface should be configured for DSP mode. A short or long frame sync is supported and ...
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Production Data AUDIO INTERFACES CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. MS selects hi-fi audio interface operation in master or slave mode. In ...
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WM8753L Figure 27 Audio Interface Configuration IFMODE[1:0] DAC DATA DAC FRAME SYNC 00 DACDAT 01 DACDAT 10 DACDAT 11 DACDAT Table 50 Hi-FI DAC Audio Interface Configuration IFMODE[1:0] ADC DATA ADC FRAME SYNC 00 VXDOUT 01 ADCDAT 10 ADCDAT 11 ...
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Production Data REGISTER ADDRESS R4 (04h) Digital Audio Interface Format Table 53 Audio Data Format Control Note: Right Justified mode does not support 32-bit data. REGISTER ADDRESS R7 (07h) Digital Interface Control Table 54 BCLK and VXCLK Master Mode Rate ...
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WM8753L PMS selects Voice audio interface operation in master or slave mode. In Master mode VXCLK and VXFS are outputs. The frequency set by the sample rate control bits SRMODE and PSR. In Slave mode VXCLK and ...
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Production Data REGISTER ADDRESS R5 (05h) Digital Interface Control Table 56 Audio Interface Control Control bits VXCLKTRI, BCLKTRI, VXDTRI and ADCDTRI configure the Hi-Fi and Voice interface pins BCLK, VXCLK, ADCDAT and VXDOUT as inputs or tristate. This allows the ...
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WM8753L Table 58 Control Interface Mode Selection 3-WIRE SERIAL CONTROL MODE In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on GPIO5/CSB latches in a complete control word consisting ...
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Production Data Figure 29 2-Wire Serial Control Interface The WM8753L has two possible device addresses, which can be selected using the GPIO5/CSB pin. The pin is sampled at power-up and selects the device address. After power-up the pin is available ...
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WM8753L READSEL STATUS REGISTER [3:1] VALUE ADDRESS 000 SR0 (0h) Device ID high 001 SR1 (1h) Device ID low 010 SR2 (2h) Device revision 011 SR3 (3h) Device capabilities 100 SR4 (4h) Device status 101 SR5 (5h) Interrupt status Table ...
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Production Data MASTER CLOCK AND PHASE LOCKED LOOP The WM8753L has two on-chip phase-locked loop (PLL) circuits that can be used to: • Generate master clocks for the WM8753L audio functions from another external clock, e.g. in telecoms applications. • ...
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WM8753L R53 (35h) PLL1 Control (1) R57 (39h) PLL2 Control (1) Table 62 PLL and Clocking Control Note: 1. PLL1RB must be set to ‘1’ before CLK1DIV2 will function PLL2RB must be set to ‘1’ before CLK2DIV2 will function The ...
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Production Data REGISTER ADDRESS R54 (36h) PLL1 Control (2) R55 (37h) PLL1 Control (3) R56 (38h) PLL1 Control (4) Table 63 PLL1 Frequency Ratio Control REGISTER ADDRESS R58 (3Ah) PLL2 Control (2) R59 (3Bh) PLL2 Control (2) R60 (3Ch) PLL2 ...
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WM8753L AUDIO SAMPLE RATES The WM8753L has two modes of operation for the HiFi DAC, ADC and voice DAC sample rates, selectable using control bit SRMODE: HiFi ADC and DAC at different sample rates Mode (IFMODE [1:0] = 11) SRMODE=0. ...
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Production Data MCLK MCLK ADC SAMPLE RATE CLKDIV2=0 CLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 12.288MHz 24.576MHz 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz ...
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WM8753L HIFI DAC + VOICE CODEC MODE In this mode the stereo ADC and voice DAC are used for voice record and playback and the HiFi DAC is used for high quality playback. The HiFi DAC may be powered off ...
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Production Data POWER MANAGEMENT The WM8753L has three control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise important to enable ...
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WM8753L REGISTER ADDRESS R22 (16h) Power Management (3) R23 (17h) Power Management (4) Table 69 Power Management w BIT LABEL DEFAULT 0 LINEMIX 0 Line mixer enable 0=LINEMIX is powered down 1=LINEMIX is powered up 8 LOUT1 0 LOUT1 enable ...
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Production Data SAVING POWER AT LOW SUPPLY VOLTAGES The analogue supplies to the WM8753L can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for ...
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WM8753L MBIASBOOST 0=x1 masterbias 1=x1.5 MICBIASBST[1:0] 00=x1 2 01=x2 micpreamp 10=x3 11=x4 micpreamp IPBIASX0P5 0=x1 local biasgen 1=x0.5 adc pga adc pga line rx & zc & zc mix mix adc adc mic mixinv mixinv detect Figure 31 Bias Current ...
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Production Data REGISTER ADDRESS R63 (3Fh) Additional control Table 72 Additional Control Register – Bias Control Bits w BIT LABEL DEFAULT 1 OPBIASX0P5 0 Analogue Output bias current control bias 1 = 0.5x bias (reduced power) 0 ...
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WM8753L REGISTER MAP ADDRESS REGISTER REMARKS (Bit 15:9) R1 (01h) 0000001 DAC Control R2 (02h) 0000010 ADC Control PCM Audio R3 (03h) 0000011 ADCDOP Interface Hi-Fi Audio R4 (04h) 0000100 Interface R5 (05h) 0000101 Interface Control Sample Rate Ctrl R6 ...
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Production Data R46 (2Eh) 0101110 ADC input mode R47 (2Fh) 0101111 Input Control (1) R48 (30h) 0110000 Input Control (2) R49 (31h) 0110001 Left Input volume R50 (32h) 0110010 Right Input volume Mic Bias comp MBVSEL 0110011 R51 (33h) control ...
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WM8753L DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type and 3. The performance of Types 0 and 1 is listed in the table below, the ...
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Production Data PARAMETER Voice ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Voice DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 75 Voice CODEC Digital Filter Characteristics PARAMETER ADC High Pass Filter (HPMODE[1:0] = 00) ...
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WM8753L DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 32 DAC Digital Filter Frequency Response – Type 0 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 34 ...
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Production Data 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 38 DAC Digital Filter Frequency Response – Type 3 Figure 39 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0 -20 -40 -60 ...
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WM8753L 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 44 ADC Digital Filter Frequency Response – Type 2 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 46 ADC Digital Filter ...
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Production Data VOICE FILTER RESPONSES VOICE DAC FILTER RESPONSES 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5 2 2.5 Frequency (Fs) Figure 48 Voice DAC Digital Filter Frequency Response 0.4 0.3 0.2 0.1 0 ...
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WM8753L DE-EMPHASIS FILTER RESPONSES -10 0 2000 4000 6000 8000 Frequency (Fs) Figure 54 De-emphasis Frequency Response (32kHz -10 0 5000 10000 Frequency (Fs) Figure 56 De-emphasis Frequency Response (44.1kHz) ...
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Production Data HIGHPASS FILTER The WM8753 has a selectable digital highpass filter in the ADC filter path to remove DC offsets. HPMODE[1: The filter response is characterised by the following polynomial – ...
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WM8753L HPMODE[1: The filter response is characterised by the following polynomial – – 0.9375z -10 -15 -20 -25 -30 0.00 0.01 0.02 0.03 Frequency (Fs) Figure 62 ADC ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 64 Recommended External Components Diagram w WM8753L PD, Rev 4.0, September 2008 88 ...
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WM8753L MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER SUPPLIES The ideal way to apply power to the WM8753 is ...
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Production Data PACKAGE DIAGRAM – 48-LEAD QFN FL: 48 PIN QFN PLASTIC PACKAGE EXPOSED GROUND PADDLE BOTTOM VIEW (A3) SIDE VIEW C SEATING PLANE W (A3 Exposed lead Half etch ...
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WM8753L PACKAGE DIAGRAM - 52-BALL BGA B: 52 BALL BGA PLASTIC PACKAGE DETAIL 2 D1 BOTTOM VIEW bbb Z aaa Z ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...