isppac-clk5520v-01tn100 Lattice Semiconductor Corp., isppac-clk5520v-01tn100 Datasheet - Page 25

• Manufacturer Part Number: isppac-clk5520v-01tn100
• Description: In-system Programmable Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GNDD pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 22. ispClock5500 Output Driver and Skew Control
Each of the ispClock5500’s output driver banks can be configured to support the following logic outputs:
To provide LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is configured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently configured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be configured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40Ω to 70Ω in 5Ω steps. A low impedance option (≈20Ω) is also provided for cases where low source ter-
mination is desired on a given output, such as when using HSTL output mode.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL output modes. Four
output slew-rate settings are provided, as specified in the “Output Rise Times” and “Output Fall Times” tables in this
data sheet.
To provide LVDS and differential LVPECL outputs, a separate driver is used which provides the correct LVDS or
LVPECL logic levels when operating from a 3.3V VCCO. Because both LVDS and differential LVPECL transmission
lines are normally terminated with a single 100Ω resistor between the ‘+’ and ‘-’ signal lines at the far end, the
• LVTTL
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
• LVDS
• Differential LVPECL (3.3V)
From V-Dividers
Adjust
Adjust
Skew
Skew
Control
Control
Control
25
OE
OE
OE
‘B’ output Driver
Single-ended
‘A’ output Driver
Single-ended
(PECL/LVDS)
Differential
Driver
ispClock5500 Family Data Sheet
BANKxA
BANKxB