isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 7

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 7. Macrocell
I/O Cell
The I/O cell of the ispMACH 5000VG device provides a high degree of flexibility. It includes the sysIO feature and
an enhanced output enable MUX for optimal performance both on- and off-chip. The sysIO feature allows I/O cells
to be configured to different I/O standards, drive strengths and slew rates. The enhanced output enable MUX pro-
vides up to 14 different output enable choices per I/O cell.
The I/O cell contains an output enable (OE) MUX, a programmable tri-state output buffer, a programmable input
buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-keeper latch.
The I/O cell receives its input from its associated macrocell. The I/O cell has a feedback line to its associated mac-
rocell and a direct path to the GRP and SRP.
The output enable (OE) MUX selects the OE signal per I/O cell. The inputs to the OE MUX are the four Shared
PTOE signals, PTOE and the two GOE signals. The OE MUX also has the ability to choose either the true or
inverse of each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to
allow easy tri-stating of the outputs for testing purposes.
The four shared PTOE signals are derived from PT163 of each GLB in the segment. The PTOE signal is derived
from the first product term in each macrocell cluster, which is directly routed to the OE MUX. Therefore, every I/O
cell can have a different OE signal. Figure 8 is a graphical representation of the I/O cell.
Shared PT Reset
Shared PT Clock
PTSA Bypass
From PTSA
Global Reset
PT Preset
PT Reset
PT Clock
BCLK0
BCLK1
BCLK2
BCLK3
D
Clk En
Clk
P
7
R/L
R
Q
ispMACH 5000VG Family Data Sheet
From
I/O Cell
Output to
I/O Block
GRP and SRP