ht82k72e Holtek Semiconductor Inc., ht82k72e Datasheet - Page 13

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ht82k72e

Manufacturer Part Number
ht82k72e
Description
Ht82k72e/ht82k72a -- One Channel Keyboard With R-f Type Mcu
Manufacturer
Holtek Semiconductor Inc.
Datasheet
the port pins from high to low. After a HALT instruction
forces the microcontroller into entering the Power Down
Mode, the processor will remain in a low-power state un-
til the logic condition of the selected wake-up pin on the
port pin changes from high to low. This function is espe-
cially suitable for applications that can be woken up via
external switches. Each pin on PA , PB, PC, PD, PE0~1
(except PE2~3) has the capability to wake-up (by nib-
ble) the device by falling edge and PE0~1 have both fall-
ing and rising wake-up function.
All I/O except PA , PB, PC, PD, PE0~1 are configured as
low to high nibble wake-up. It means once there are one
pin is in low level, the I/O cannot wake-up the MCU.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC, PDC and PE4~7 (control I/O PE0~3), to control
the input/output configuration. With this control register,
each CMOS output or input with or without pull-high re-
sistor structures can be reconfigured dynamically under
software control. Each of the I/O ports is directly
mapped to a bit in its associated port control register.
For the I/O pin to function as an input, the corresponding
bit of the control register must be written as a 1 . This
will then allow the logic state of the input pin to be di-
rectly read by instructions. When the corresponding bit
of the control register is written as a 0 , the I/O pin will
be setup as a CMOS output. If the pin is currently setup
as an output, instructions can still be used to read the
output register. However, it should be noted that the pro-
gram will in fact only read the status of the output data
latch and not the actual logic status of the output pin.
Rev. 1.00
Input/Output Ports
13
Pin-shared Functions
The flexibility of the microcontroller range is greatly en-
hanced by the use of pins that have more than one func-
tion. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be over-
come. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application pro-
gram control.
External Timer Clock Input
The external timer pin TMR is pin-shared with the I/O
pin PA2. To configure this pin to operate as timer input,
the corresponding control bits in the timer control reg-
ister must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
RFD Output
The RFD output is pin-shared with the I/O pin PC6. It
can be series connected with a capacitor to OSC1 and
to modulate the modulate the OSC frequency and
therefore be used to generate an FM modulated sig-
nal on RF_OUT to transmit data.
Z1/Z2 Pin
The Z1/Z2 is for Z_axis function, it is pin shared with
the PE0/PE1 pins. PE0, PE1 has falling and rising
edge wake-up function, if it select can wake-up by
OTP option. In halt mode if PE0 wake-up the PG6
[1EH] will be set, if PE1 wake-up the PG7 [1EH] will be
set.
If user read PG6 or PG7, the bit will be clear.
HT82K72E/HT82K72A
February 20, 2008

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