ht82k73e Holtek Semiconductor Inc., ht82k73e Datasheet - Page 24

• Manufacturer Part Number: ht82k73e
• Description: 2.4ghz Keyboard Tx 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the HALT
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Each pin on Port A or any nibble on the other ports can
be setup via configuration options to permit a negative
transition on the pin to wake-up the system. When a port
pin wake-up occurs, the program will resume execution
at the instruction following the HALT instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the interrupt
is disabled or the interrupt is enabled but the stack is full,
in which case the program will resume execution at the
instruction following the HALT instruction. In this situa-
tion, the interrupt will not be immediately serviced, but
will rather be serviced later when the related interrupt is
finally enabled or when a stack level becomes free. The
other situation is where the related interrupt is enabled
and the stack is not full, in which case the regular inter-
rupt response takes place. If an interrupt request flag is
set to ²1² before entering the Power Down Mode, the
wake-up function of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Rev. 1.00
An external reset
An external falling edge on any of the I/O pins
A system interrupt
A WDT overflow
24
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by its own internal dedicated internal
WDT oscillator. Note that if the WDT configuration op-
tion has been disabled, then any instruction relating to
its operation will result in no operation.
All Watchdog Timer options, such as enable/disable,
WDT clock source and clear instruction type all selected
through configuration options. There are no internal reg-
isters associated with the WDT in this device. However,
it should be noted that this specified internal clock pe-
riod can vary with VDD, temperature and process varia-
tions. Whether the WDT clock source is its own internal
WDT oscillator, it is further divided by an internal 6-bit
counter and a clearable single bit counter to give longer
Watchdog time-outs. As the clear instruction only resets
the last stage of the divider chain, for this reason the ac-
tual division ratio and corresponding Watchdog Timer
time-out can vary by a factor of two.
The exact division ratio depends upon the residual value
in the Watchdog Timer counter before the clear instruc-
tion is executed. It is important to realise that as there
are no independent internal registers or configuration
options associated with the length of the Watchdog
Timer time-out, it is completely dependent upon the fre-
quency the internal WDT oscillator.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a HALT instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle CLR WDT instruction while the second is to use the
two commands CLR WDT1 and CLR WDT2. For the first
option, a simple execution of CLR WDT will clear the
WDT while for the second option, both CLR WDT1 and
CLR WDT2 must both be executed to successfully clear
the WDT. Note that for this second option, if CLR WDT1
is used to clear the WDT, successive executions of this
instruction will have no effect, only the execution of a
CLR WDT2 instruction will clear the WDT. Similarly after
the CLR WDT2 instruction has been executed, only a
successive CLR WDT1 instruction can clear the Watch-
dog Timer.
HT82K73E
April 16, 2008