m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 7

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m52s128168a-7tig

Manufacturer Part Number
m52s128168a-7tig
Description
2m X 16 Bit X 4 Banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
ESMT
AC Timing Parameter & Specifications-continued
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE
command
Row Cycle Time
AUTO REFRESH Row Cycle
Time
ACTIVE to READ,WRITE
delay
PRECHARGE command
period
Minimum t
ACTIVE bank A to ACTIVE
bank B command
Write recovery time
Write data in to READ
command delay
Col. Address to Col. Address
delay
Average periodic refresh
interval
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble
setup time
Load Mode Register /
Extended Mode register
cycle time
Exit self refresh to first valid
command
Exit power-down mode to
first valid command
Autoprecharge write
recovery+Precharge time
Elite Semiconductor Memory Technology Inc.
Parameter
CKE
High/Low time
Symbol
t
t
t
WPRES
t
t
t
t
t
t
t
t
t
t
t
WPRE
WPST
t
t
RPRE
t
t
RPST
t
WTR
t
QHS
t
RCD
t
RRD
CCD
REFI
MRD
t
RAS
RFC
CKE
XSR
DAL
WR
HP
QH
RC
RP
XP
t
CL
t
Preliminary
min or t
HP
(t
(t
min-t
WR
RP
67.5
22.5
22.5
0.25
min
120
0.4
0.9
0.4
45
80
15
15
25
2
1
1
0
2
+
-
-
/t
/t
CK
CK
CH
QHS
)
)
min
-7.5
max
0.75
15.6
70K
0.6
1.1
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
CL
t
min or t
HP
(t
(t
min-t
WR
RP
0.25
min
120
0.4
0.9
0.4
50
80
90
30
30
15
15
25
2
1
1
0
2
+
-
-
/t
/t
CK
CK
CH
QHS
)
)
Revision : 1.4
Publication Date : Sep. 2008
min
-10
M53D128168A
max
15.6
70K
1.0
0.6
1.1
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7/47
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK

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