74LVT14D,112 NXP Semiconductors, 74LVT14D,112 Datasheet

IC HEX INVERTER/SCHM TRIG 14SOIC

74LVT14D,112

Manufacturer Part Number
74LVT14D,112
Description
IC HEX INVERTER/SCHM TRIG 14SOIC
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT14D,112

Number Of Circuits
6
Logic Type
Inverter with Schmitt Trigger
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Inputs
1
Current - Output High, Low
20mA, 32mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Logic Family
74LVT
High Level Output Current
- 20 mA
Low Level Output Current
32 mA
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.7 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1593-5
74LVT14D
935209170112
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LVT14D
74LVT14DB
74LVT14PW
74LVT14BQ
Ordering information
Package
Temperature range Name
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
The 74LVT14 is a high-performance BiCMOS product designed for V
It is capable of transforming slowly changing input signals into sharply defined, jitter free
output signals. In addition, it has a greater noise margin than conventional inverters.
Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase
splitter driving a TTL totem-pole output. The Schmitt trigger uses positive feedback to
effectively speed-up slow input transitions, and provide different input threshold voltages
for positive-going and negative-going inputs. The threshold differential (typically 600 mV)
is determined internally by resistor ratios and is insensitive to temperature and supply
voltage variations.
I
I
I
I
I
I
I
74LVT14
3.3 V hex inverter Schmitt trigger
Rev. 02 — 25 April 2008
Different positive and negative going input threshold voltages
Tolerant of slow input transitions
High noise immunity
TTL input and output switching levels
Output capability: +32 mA/ 20 mA
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
N
N
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
SO14
SSOP14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
Description
plastic small outline package; 14 leads;
body width 7.5 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
thin quad flat package; no leads; 14 terminals;
body 2.5
4.5
0.85 mm
Product data sheet
CC
operation at 3.3 V.
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1

Related parts for 74LVT14D,112

74LVT14D,112 Summary of contents

Page 1

V hex inverter Schmitt trigger Rev. 02 — 25 April 2008 1. General description The 74LVT14 is a high-performance BiCMOS product designed for capable of transforming slowly changing input signals into sharply defined, jitter free ...

Page 2

... NXP Semiconductors 4. Functional diagram mna204 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74LVT14 GND Fig 4. Pin configuration for SO14 and (T)SSOP14 74LVT14_2 Product data sheet 001aac497 Fig 2. IEC logic symbol 001aah920 Fig 5. Rev. 02 — 25 April 2008 3.3 V hex inverter Schmitt trigger ...

Page 3

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 11 10, 12 GND Functional description Table 3. Function selection Inputs [ HIGH voltage level LOW voltage level. 7. Limiting values [1] Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I I HIGH-level output current OH I LOW-level output current OL T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL [1] Typical values are measured at T 11. Waveforms See Table 8 for measurement points. V and V are typical output voltage levels that occur with the output load ...

Page 6

... NXP Semiconductors Table 8. Measurement points 3.6 V Test data is given in given in Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 8. Load circuitry for switching times Table 9. Test data ...

Page 7

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 8

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 10. Package outline SOT337-1 (SSOP14) ...

Page 9

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 10

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 11

... Release date 74LVT14_2 20080425 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Quick reference section removed. • ...

Page 12

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Revision history ...

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