ak4543 AKM Semiconductor, Inc., ak4543 Datasheet
ak4543
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ak4543 Summary of contents
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... Rev 2.1 Multimedia Audio CODEC The AK4543 is a 18bit high performance codec compliant with Audio Codec ’97 Rev 2.1 requirements. The AC Link serial interface allows the AK4543 to be used with digital controllers as well as custom logic accelerators to meet full PC98 and PC99 requirements for a PCI audio solution. ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI setup delay BIT_CLK SDATA_IN SDATA_OUT SYNC n n <M0046-E-01> T hold - 9 - [AK4543 1999/01 ...
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... All AC-link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the rising edge of RESET# causes the AK4543 AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Note that the AK4543 enters in the ATE test mode regardless SYNC is high or low. ...
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... If a slot is “Tagged” invalid the responsibility of the source of the data, (The AK4543 for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AK4543 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit) ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... BIT_CLK, the AK4543 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AK4543 transitions SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC ’ ...
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... KASEI] <M0046-E-01> [AK4543] 1999/01 ...
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... X X REF ANL DAC ADC writes a “01xxxxx” the AK4543 1999/01 Default 2D50h 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h na x200h 414Bh 4D02h ...
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... KASEI] n The PC Beep is routed to L & R Line outputs directly when AK4543 RESET State(Reset# is “L”). This is so that Power on Self Test(POST) codes can be heard by the user in case of a hardware problem with the PC. After Reset# goes “H”, direct PC beep pass thru becomes OFF ...
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... KASEI <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI <M0046-E-01> [AK4543] 1999/01 ...
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... Play Vendor ID code with upper byte of 7Ch register, the first character of that id, lower byte of 7Ch register, the second character and upper byte of 7Eh register the third character. These three characters are ASCII encoded. Lower byte of 7E register is for the Vendor Revision number. <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] AK4543 Block Diagram PC_VOL (0A[4:1]) PC_BEEP GAIN (0C[5:0]) PHONE LINE_IN_ GAIN(10[12:8]) LINE_IN_R GAIN (10[4:0]) CD_L GAIN (12[12:8]) CD_GND GAIN (12[4:0]) CD_R GAIN (14[12:8]) VIDEO_L GAIN (14[4:0]) VIDEO_R GAIN (16[12:8]) AUX_L AUX_R GAIN (16[4:0]) (0E[6]) MIC1 GAIN (0E[5:0]) 20dB MIC2 Mux (20[8]) PD 26[11] Voltage Reference Vref VRADDA AVdd1 AVss1 <M0046-E-01> PD 26[10] PD 26[10] AK4543 Mixer ...
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... The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC ‘97 controller will send a pulse on the sync line issuing a warm reset. This will restart the AK4543 digital (resetting PR4 to zero). The AK4543 can also be woken up with a cold reset ...
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... KASEI] PR0=1 ADCs off Normal PR0=0 & ADC=1 AK4543 Powerdown/Powerup flow with analog still alive n Digital Controller BIT_CLK SDATA_OUT RESET# SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 <M0046-E-01> PR1=1 PR4=1 Digital DACs off I/F PR0 PR1 off PR4 PR1=0 & Warm Reset DAC=1 AC ‘97 ...
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... Regardless of the test mode, the AC ‘97 controller must issue a “Cold” reset to resume normal operation of the AC ‘97 Codec. Test Mode Functions ATE in circuit test mode When AC ‘97 is placed in the ATE test mode, its digital AC-link outputs (i.e. BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in circuit testing of the AC ‘97 controller. <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] The following figure shows the system connection diagram. Primary codec: codec ID1:codecID0=0:0 AVDD: 5V DVDD: 3. 3.3V : 48pin open 5.0V : 48pin DGND <M0046-E-01> System Design - 26 - [AK4543] 1999/01 ...
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... KASEI] Secondary codec codec ID1:codecID0=0:1,1:0 or 1:1 This figure is the case of ID1 =0 and ID0=1. AVDD: 5V DVDD: 3. 3.3V : 48pin open 5.0V : 48pin DGND <M0046-E-01> [AK4543] 1999/01 ...
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... KASEI] LINE_IN_L LINE_IN_R separated from other non-used input pins. <M0046-E-01> J15 [AK4543] 1999/01 ...
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... KASEI] 48pin P 9.0 + 0.2 7 0.19 + 0.05 <M0046-E-01> Package 1 1 0.01M 0 10 0.5 + 0.2 0. [AK4543] 0.10 + 0.07 0.17 + 0.05 1999/01 ...
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... KASEI] 1) Pin #1 indication 2) Date Code : XXXXXXX (7 digits) 3) Marketing Code : AK4543VQ 4) Country of Origin 5) Asahi Kasei Logo <M0046-E-01> Marking AK4543VQ XXXXXXX JAPAN [AK4543] 1999/01 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <M0046-E-01> Appendix IMPORTANT NOTICE - 31 - [AK4543] 1999/01 ...