ml70512 Oki Semiconductor, ml70512 Datasheet
ml70512
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ml70512 Summary of contents
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... Bluetooth Baseband Controller IC GENERAL DESCRIPTION The ML70512 is a CMOS digital IC for use in 2.4 GHz band Bluetooth™ systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Since the ML70512 has Oki’s Bluetooth protocol stack software installed, when the IC is used in conjunction with the Bluetooth RF transceiver IC, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems ...
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... Timers 16-bit auto reload timer (1ch) 18-bit auto reload timer (3ch) Interrupt controller 11 causes Clock control circuit Crystal oscillator circuit (12 MHz, 13 MHz MHz, 32 kHz or 32.768 kHz) Internal PLL FEDL70512-04 6.22 mm 0.48 mm; pin pitch: 0.50 mm 1.5 mm; pin pitch: 0.80 mm) (CX72303) ML70512 2 C bus 2/29 ...
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... OKI Semiconductor PIN PLACEMENT ML70512HB: 83-pin WCSP (P-VFLGA83-6.22 6.22-0.50-W) Core GND SCLKO VDD 10 PCM GND GND OUT 9 Core CIO3 GND VDD 8 Core GND SIN VDD 7 SFRQ CIO6 VDD SEL1 6 GND LVDD SOUT 5 PLL_ RSSI VDD CLK _CLK 4 PLL_ PLL_ DATA POW 3 PLL_ ...
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... PCMCLK OUT Core VDD VDD SCLKO NC CIO6 NC SFRQ CIO3 GND GND LVDD VDD SEL1 Core GND SOUT SIN GND GND VDD TOP VIEW FEDL70512-04 ML70512 RTS CIO2 CIO1 (SDA) VDD Core VDD PCM SYNC Core VDD GND VDD K 4/29 ...
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... CX72303: RF-LSI receiving C4 C2 BCM2002X: System clock request ML70561: System clock request ML7050: Local PLL power control 0: Assert, 1: Negate CX72303: PA Power control Negate, 1: Assert BCM2002X: Select serial transmit mode ML70561: Select serial transmit mode FEDL70512-04 ML70512 Description clock characteristic control 5/29 ...
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... ML70512HB ML70512LA ML7050: Transmit enable 0: Assert, 1: Negate CX72303: Transmit enable Negate, 1: Assert BCM2002X: Serial write data ML70561: Serial write data ML7050: Receive enable 0: Assert, 1: Negate CX72303: Receive enable Negate, 1: Assert BCM2002X: Receive enable ML70561: Receive enable FEDL70512-04 ML70512 Description 6/29 ...
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... BCM crystal frequency select pins SFRQSEL [1:0] *[1] *[ RF-LSI select pins RFSEL[2:0] 001 010 *[3] *[4] 011 101 Others FEDL70512-04 ML70512 Description 1: Negate characteristic control 1: Closed loop Description SCLK BCM input crystal frequency frequency (RFSEL (RFSEL = 101) 101) 13 MHz 19.68 MHz 12 MHz 19 ...
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... D10 K4 Initial setting: input (can be switched by an internal register) PCM clock (64 kHz/128 kHz Initial setting: input (can be switched by an internal register) Pin Placement ML70512HB ML70512LA B5 E1 ACE transmit serial data B7 F1 ACE receive serial data J10 K9 ACE transmit data ready H6 ...
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... G8 K8 General port (initial state: input General port (initial state: output General port (initial state: output General port (initial state: input General port (initial state: input) Pin Placement ML70512HB ML70512LA — [*4] No connection FEDL70512-04 ML70512 Description Description 9/29 ...
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... I/O power supply pin 2.70 to 3.6 V Power supply pin for internal circuit [*7] [*8] 1.65 to 1.95 V RF-I/O power suply pin (Same voltage the V DD [*9] [*10] Digital block ground pin [*11] [*12] Analog block power supply pin 1.65 to 1.95 V [*13] [*14] [*15] [*16] Analog block ground pin [*17] [*18] FEDL70512-04 ML70512 Description for RF-LSI) 10/29 ...
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... OKI Semiconductor BLOCK DIAGRAM Clock FEDL70512-04 ML70512 ML70512 DETACH UART I/F GPIO I/F 11/29 ...
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... Receive clock re-timing function • FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function Tx SCO Buffer Packet Composer Tx ACL Buffer FHCNT Security Timing Rx SCO Buffer Packet Decomposer Rx ACL Buffer FEDL70512-04 ML70512 RF LSI TXD RF CNT CNT RXD 12/29 ...
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... Packet decomposition (separating the packet header and the payload) - Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation) - Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) • Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function FEDL70512-04 ML70512 13/29 ...
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... Error servicing for parity, overrun, and framing errors • Configuration of 1 Data Frame during Reception SIN Start SAMPLE CLK • Configuration of 1 Data Frame during Transmission SOUT 5 data bits to Stop Parity 8 data bits 5 data bits to Start Stop Parity 8 data bits FEDL70512-04 ML70512 14/29 ...
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... Data is shifted in on the falling edge of CLK PCMSYNC(I) 8 bits or 16 bits DATA DATA DATA DATA DATA DATA 125 s (8kHz) 8 bits or 16 bits DATA DATA DATA DATA DATA DATA 125 s (8kHz) FEDL70512-04 ML70512 LSB MSB DATA LSB MSB DATA LSB MSB DATA LSB MSB DATA 15/29 ...
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... Data is shifted in on the falling edge of CLK DATA DATA DATA 3 125 s (8kHz) 8 bits or 16 bits DATA DATA DATA Data is shifted in on the falling edge of CLK. DATA DATA DATA 62.5 s (Max.) 125 s (8kHz) FEDL70512-04 ML70512 LSB MSB DATA LSB MSB DATA LSB MSB DATA LSB MSB DATA 16/29 ...
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... Vi = GND to 3.6 V – Pull-down Vi = GND –200 50 k Pull- GND to V – Pull-down Iddo During 24 MHz operation 0 Idds CLK stopped — FEDL70512-04 ML70512 Unit 0.62 W °C Typ. Max. Unit 3.3 3.6 V 1.8 1.95 V — — 0.8 V — ...
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... TX:DH1/DM1 RX:DH5/DM5 — 19.6 TX:DH1/DM1 Tmc1 (V = 2.7 to 3.6V, CoreV = 1.65 to 1.95V -40 to 85° Description Tmp0 Tmp1 (V = 2.7 to 3.6V, CoreV = 1.65 to 1.95V -40 to 85° Description FEDL70512-04 ML70512 Max. Unit — — — — mA — — — — Min Typ Max Unit ...
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... Reset pulse width RESW Note : Apply "L" to the RESET pin for 10 sec or more after the power supply has been settled. Power supply stable period T RESW (V = 2.7 to 3.6V, CoreV = 1.65 to 1.95V -40 to 85° Description Min 10 FEDL70512-04 ML70512 Typ Max Unit — — s 19/29 ...
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... V DD 0. Tpc0 Tpc1 Tpc2 Tpc4 Tpc3 Tpc6 Tpc5 Tpc 7 Tpc 8 (Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V -40 to 85°C) Description 0.8V DD 0.2V DD FEDL70512-04 ML70512 Tpc2 Tpc4 Tpc7 Min Typ Max Unit 100 — — ns 100 — — ns — — 250 ns 100 — — ...
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... F VDD GND Capacitors should locate close to LSI pins. Example of ML70512 voltage supply circuit • Insert appropriate bypass capacitors between the V Note 1: Precautions to insert the bypass capacitors - Use traces of V and GND lines wider than those of the other signal lines. ...
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... The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information recommended to determine the final circuit values including the capacitance of the circuit board designed by the user. ML70512 R2 R3 X’tal Connect this oscillator circuit only when connecting the OKI RF-LSI ML7050. FEDL70512-04 ML70512 22/29 ...
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... It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands. For command details, contact Oki Electric Industry Co., Ltd MHz clock is input to external pin SCLKP MHz clock is input to external pin SCLKP MHz clock is input to external pin SCLKP. FEDL70512-04 ML70512 23/29 ...
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... GND PCM I/F Pin Name Process When Pin Not Used PCMIN Open or V PCMSYNC Open or GND PCMCLK Open or GND Processes of Other Pins TEST I/F etc. Pin Name Process When Pin Not Used DETACH Pull FEDL70512-04 ML70512 Comments Comments Comments Comments 24/29 ...
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... OKI Semiconductor FEDL70512-04 ML70512 25/29 ...
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... OKI Semiconductor PACKAGE DIMENSIONS ML70512HB - 83pinWCSP (P-VFLGA83-6.22 P-VFLGA83-6.22×6.22-0.50-W 5 Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information. Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. ...
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... OKI Semiconductor ML70512LA - 84pin BGA (P-LFBGA84-0909-0.80) P-LFBGA84-0909-0.80 5 Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information. Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. ...
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... Section. Partially eliminated the contents of “ Characteristics” Section. Partially eliminated the contents of “Power 18 18 Supply Current (IDDO) Characteristics by Power Saving Mode” Section. Partially eliminated the contents of “Setting 23 23 the Reset” Section. FEDL70512-04 ML70512 Description the contents of 28/29 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL70512-04 ML70512 Copyright 2003 Oki Electric Industry Co., Ltd. 29/29 ...