ml7000 Oki Semiconductor, ml7000 Datasheet
ml7000
Related parts for ml7000
ml7000 Summary of contents
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... ML7001-01 Single Rail CODEC GENERAL DESCRIPTION The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging from 300 to 3400 Hz with filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the devices are optimized for ISDN terminals, digital wireless systems, and digital PBXs. ...
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... LPF AIN+ GSX SGC SG GEN SG – VFRO + PWI – AOUT– + – AOUT+ + 8th A/D TCONT BPF CONV. AUTO PLL ZERO VR GEN RTIM 5th D/A LPF CONV. RCONT PWD PWD Logic FEDL7000-03 ML7000-01/ML7001-01 PCMOUT XSYNC BCLK RSYNC ALAW PCMIN PDN 2/20 ...
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... AIN– AOUT– GSX PWI VFRO ALAW PDN RSYNC 9 15 BCLK PCMIN 10 14 XSYNC 20-Pin Plastic SSOP 13 PCMOUT FEDL7000-03 ML7000-01/ML7001-01 20 SGC 19 AIN+ 18 AIN– 17 GSX ALAW BCLK 12 XSYNC 11 PCMOUT 3/20 ...
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... Characteristics Adjustment Circuit variable GSX R2 > AIN– R2 – C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) AIN > AIN > AIN– – R5 > GSX C2 > ¥ 3.14 ¥ 30 ¥ R5 for ML7000-01 and 2 FEDL7000-03 ML7000-01/ML7001-01 for ML7001-01 above PP 4/20 ...
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... AOUT Power supply for +5 V (ML7000-xx (ML7001-xx) PCMIN PCM data input. A serial PCM data input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The data rate of PCM is equal to the frequency of the BCLK signal. ...
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... Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. FEDL7000-03 ML7000-01/ML7001-01 6/20 ...
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... A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. When A-law is selected, the ML7000-01 and ML7001-01 output the character signal, inverting the even bits. Input/Output Level ...
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... Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is 300 mA for ML7000-01 and 200 mA for ML7001-01. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power-saving or power-down mode. ...
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... Receive Sync Pulse Setting Time RSYNC Setup Time RSYNC Hold Time PCMIN Setup Time PCMIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width Values above the dotted line are for ML7000-01; those below, for ML7001-01. Symbol Condition V — — ...
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... High Level Input Leakage Current High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance Values above the dotted line are for ML7000-01; those below, for ML7001-01. (ML7001-01: V (ML7000-01: V Condition Operating mode ...
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... Parameter Symbol Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Values above the dotted line are for ML7000-01; those below, for ML7001-01. Receive Analog Interface Characteristics Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Values above the dotted line are for ML7000-01 ...
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... Transmit Frequency Response Receive Frequency Response Transmit Signal to Distortion Ratio Receive Signal to Distortion Ratio Transmit Gain Tracking Receive Gain Tracking *1 Psophometric filter is used. Values above the dotted line are for ML7000-01; those below, for ML7001-01. (ML7001-01 kHz (ML7000-01 kHz Freq ...
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... Crosstalk Attenuation *1 Psophometric filter is used. *2 Input "0" code to PCMIN. *3 AVR is defined at VFRO output. *4 With respect to minimum value of the group delay distortion. Values above the dotted line are for ML7000-01; those below, for ML7001-01. (ML7001-01 kHz (ML7000-01 kHz Freq ...
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... Semiconductor AC Characteristics (Continued) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Digital Output Delay Time *5 Measured under idle channel noise. (ML7001-01 kHz (ML7000-01 kHz Freq. Level Symbol Condition (Hz) (dBm0) 4.6 kHz DIS ...
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... XSYNC t XD1 PCMOUT MSD Receive Timing BCLK RSYNC PCMIN MSD Figure 1 Basic Timing FEDL7000-03 ML7000-01/ML7001- XD2 15/20 ...
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... AOUT– PWI VFRO 0.1 mF PDN SGC FEDL7000-03 ML7000-01/ML7001-01 PCM signal output 8 kHz SYNC signal input PCM shift clock input PCM signal input Control of companding law 1: A-law 0: m-law Power down control input 1: Normal operation 0: Power down PCM signal output ...
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... Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. pin not lower than –0.3 V even instantaneously to avoid latch- FEDL7000-03 ML7000-01/ML7001-01 17/20 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7000-03 ML7000-01/ML7001-01 Package material Epoxy resin Lead frame material 42 alloy Solder plating (≥ ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7000-03 ML7000-01/ML7001-01 Package material Epoxy resin Lead frame material ...
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...