ml7029b Oki Semiconductor, ml7029b Datasheet
ml7029b
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ml7029b Summary of contents
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... D S ATA HEET Multifunction ADPCM CODEC ML7029B May 2004 T S ...
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... ML7029B Multifunction ADPCM CODEC DESCRIPTION The ML7029B is a single channel ADPCM CODEC IC which performs mutual transcoding between the analog voice band signal and 32 kbps ADPCM serial data. FEATURES • Single 3 V Power Supply Operation (VDD: 2.7 to 3.6 V) • ADPCM Algorithm: ITU-T G.726 (32 kbps) • ...
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... Semiconductor BLOCK DIAGRAM A/D AIN– Conv GSX VFRO 20 k VREF SG CR2-B7 CR2- BPF TXON/ OFF CR3- CR2-B3 D/A LPF Conv. CR2- ML7029B PCM PCMSO Compander PCMSI IS ADPCM IR PCMRO PCM RXON/ PCMRI Expander OFF BCLK SYNC MCU I/F 2/24 ...
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... PIN CONFIGURATION (TOP VIEW) GSX AIN– VFRO PDN 15 NC: No Connection 30-Pin Plastic SSOP ML7029B BCLK 28 SYNC 27 PCMSO 26 PCMSI PCMRO 22 PCMRI MCK 19 DEN 18 EXCK 17 DIN 16 DOUT 3/24 ...
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... The reset width (a “L” level period) should be 200 ns or more. Be sure to reset the control registers by executing this power down to keep this pin to digital “0”level for 200 ns or longer after the power is turned on and V ). The V A exceeds 2 ML7029B pin must be kept as close D 4/24 ...
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... This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure 1. BCLK Shift clock input for the PCM and ADPCM data. The frequency is set in the range 256 times the SYNC frequency. Refer to Figure 1. ML7029B 5/24 ...
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... Sampling input for the PCM and ADPCM data. The frequency is 8 kHz. Synchronize this signal with BCLK signal. SYNC is used to indicate the MSB of the PCM data stream. Refer to Figure 1. SYNC BCLK PCMSO/PCMSI/ MSB PCMRO/PCMRI IS/IR MSB Figure 1 PCM and ADPCM Interface Basic Timing 125 s LSB LSB ML7029B 6/24 ...
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... High Impedance (a) Data Write Timing Diagram (b) Data Read Timing Diagram High Impedance (a) Data Write Timing Diagram (b) Data Read Timing Diagram ML7029B 7/24 ...
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... PDN — — ALL RESET RESET MUTE GAIN1 GAIN0 ON/OFF Side Tone — — GAIN0 Condition — — — — stg ML7029B R R/W — — — — R/W MUTE PAD R/W GAIN2 GAIN1 GAIN0 — TEST2 TEST3 R/W Rating Unit – ...
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... CLK Digital Input Pins ir Digital Input Pins if BCLK SYNC (see Fig. 3-1) BCLK SYNC (see Fig. 3-2) SYNC (see Fig. 3-1) SYNC (see Fig. 3-2) — S — H Digital Output Pins ML7029B Min. Typ. Max. +2.7 3.0 +3.6 –25 +25 +70 V — — 0. — 10.368 — ...
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... GSX, VFRO L C GSX, VFRO L V GSX, VFRO ( GSX, VFRO 10+0 (Rise time to max. 90% level) PP ML7029B (V = 2 –25 to +70°C) DD Min. Typ. Max. Unit — 6 — 0.01 0.1 mA — — 2.0 µA — — 0.5 µA 2.1 — ...
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... Hz – 1020 Hz –40 AIN– — (*4) 1020 Hz(GSX) 0 1020 Hz(VFRO) 0 ML7029B = 2 –25 to +70°C) Min. Typ. Max. Unit 30 — — dB –0.5 — 1.5 dB Reference dB –0.5 — 1 — — dB –0.5 — ...
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... Fig. 4 Fig. 4 EXCK EXCK EXCK Symbol Condition D All stages, to programmed value G ML7029B (V = 2 –20 to +70°C) DD Min. Typ. Max. Unit 0 — 200 ns 0 — 200 ns 0 — 200 ns 0 — 200 ns 50 — ...
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... XD1 MSB PCMSO t SDX IS MSB t SDX Receive Side PCM/ADPCM Data Interface BCLK SYNC t RD1 MSB PCMRO SDR MSB IR Figure 3-1 PCM/ADPCM Data Interface (Continuous BCLK XD2 t XD3 LSB RD2 RD3 LSB ML7029B t XD3 LSB t RD3 LSB 13/24 ...
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... SB t SYNC t XD1 MSB PCMSO IS MSB Receive Side PCM/ADPCM Data Interface BCLK SYNC t t RD2 RD1 MSB PCMRO MSB Figure 3-2 PCM/ADPCM Data Interface (Burst Mode Clock) WSB t XD2 t XD3 LSB t RD3 t DH LSB ML7029B t XD3 LSB t RD3 LSB 14/24 ...
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... Figure 4-2 Serial Control Port Interface (DIN = 16 bits ML7029B 15/24 ...
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... They must be reset at the same time PDN ALL — — 0/Power-on, 1/Power-down RESET RX RESET TX MUTE RX MUTE Reset* 1/Mute 1/Mute 1/inserted in the receive side voice path loss 0/no PAD s or more. ML7029B — — — — RX PAD 16/24 ...
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... Transmit Gain B2 B1 – – – ML7029B GAIN2 RX GAIN1 RX GAIN0 Receive Gain 0 – – – 17/24 ...
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... B1,B0:It is Test Resister for LSI. It should be set to “0” during normal operation Side Tone — — GAIN0 Side Tone Path Gain 0 0 OFF 0 1 – – – – – – –9 dB ML7029B — TEST2 TEST3 * 0 0 18/24 ...
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... Power-down GSX AIN– ML7029 VFRO PDN 15 ML7029B PCM I/F BCLK 29 SYNC 28 PCMSO 27 PCMSI 26 ADPCM DATA PCMRO 23 PCMRI Master Clock MCK 20 DEN 19 EXCK 18 MCU I/F ...
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... MIN. 1-bit clock : MAX. (Number of clocks in burst mode)–1 1/f s sample PCM Data Input 1 s (Range of Data Slip Occurrence) A 0.83/f s sample Figure 6 1/f s sample ADPCM Data Input 1 s (Range of Data Slip Occurrence) s sample B Figure 7 ML7029B 20/24 ...
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... The data slip occurs at the timing of 1 and 2 above. Therefore, taking internal clock jitters and IC internal delay into consideration, the timing of SYNC and BCLK signals should not be set up in the range of about 1 s from the timing A and B. Latch ADPCM COD A Internal Clock Generation ADPCM DEC Latch Figure 8 ML7029B Latch P (2) Latch S/P IR 21/24 ...
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... Transmit Frequency Characteristics 10 0 -10 -20 -30 -40 -50 -60 -70 -80 100 Figure 9 Transmit Bandpass Filter Characteristic Receive Frequency Characteristics 10 0 -10 -20 -30 -40 -50 -60 -70 -80 100 Figure 13 Receive Lowpass Filter Characteristic Transmit BPF Characteristic 1000 Frequency (Hz) Receive LPF Characteristic 1000 Frequency (Hz) ML7029B 10000 10000 22/24 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ML7029B (Unit: mm) Package material Epoxy resin Lead frame material ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Semiconductor ML7029B 24/24 ...
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Oki R EGIONAL Northwest Area Southwest and South Central Area 785 N. Mary Avenue Sunnyvale, CA 94085 1902 Wright Place, Suite 200 Tel: 408/720-1900 Carlsbad, CA 92008 Fax: 408/720-8965 Tel: 760/918-5830 Fax: 760/918-5505 Northeast Area Southeast Area Shattuck Office Center ...