ml7037-003 Oki Semiconductor, ml7037-003 Datasheet
ml7037-003
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ml7037-003 Summary of contents
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... Transmission signal equalizer • Package : 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) (ML7037-003TB) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * This is a digest version of the ML7037-003 datasheet. Ask an OKI sales for a full version before you start actual designing activities (typ.) for white noise : Tlined = (typ.) for white noise ...
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... OKI Semiconductor BLOCK DIAGRAM PEDL7037-003-01Zz_Digest Figure 1 ML7037-003 REGOUT0, 1 REGOUT0, 1 VBG VBG PDN PDN DOUT DOUT DIN DIN EXCK EXCK DEN DEN MCUSEL MCUSEL GPOC7 GPOC7 GPOC6 GPOC6 GPOC5 GPOC5 GPOC4 GPOC4 GPOC3 GPOC3 GPOC2 GPOC2 GPOC1 GPOC1 GPOC0 GPOC0 RST RST ...
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... GPOC3 53 GPOC4 54 GPOC5 55 GPOC6 56 GPOC7 57 CLKSEL 58 RST CK/XI 62 TSTI1 63 TSTI2 64 64-Pin Plastic TQFP Figure 2 PEDL7037-003-01Zz_Digest ML7037-003 M CUSEL 32 DEN 31 EXCK 30 DIN 29 DOUT 28 GPIA7 (RPAD3) 27 GPIA6 (RPAD2) 26 GPIA5 (RPAD1) 25 GPIA4 (RPAD0) 24 GPIA3 (TPAD3) 23 GPIA2 (TPAD2) 22 GPIA1 (TPAD1) 21 GPIA0 (TPAD0) 20 AVREFEN ...
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... General-purpose input port pin ＜Primary function＞ General-purpose input port pin I ＜Secondary function＞ Input pin to tune volume of transmit speech signals General-purpose input port pin ＜Primary function＞ I General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of transmit speech signals PEDL7037-003-01Zz_Digest ML7037-003 4/41 ...
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... General-purpose input port pin ＜Secondary function＞ Input pin to select output signals from AVFRO/LVFRO General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to select noise canceler mode between normal mode and through mode PEDL7037-003-01Zz_Digest ML7037-003 5/41 ...
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... PCM data input pin line-side PCMdata output pin Input pin to select speech digital interface coding format between 16bit Linear PCM and -law PCM General-purpose output port pin General-purpose output port pin General-purpose output port pin General-purpose output port pin PEDL7037-003-01Zz_Digest ML7037-003 6/41 ...
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... Input pin to select between clock slave mode and clock master mode for PCM interface Reset pin Power-down pin Ouput pin to connect a crystal unit for master clock Input pin to connect a crystal unit for master clock Master clock input pin Test pin1 Test pin2 PEDL7037-003-01Zz_Digest ML7037-003 7/41 ...
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... AIN1N (AMP1) Gain-Max（AMP1）≦5 times (+13.97dB) AGSX0 R2 AIN0N AIN0P (AMP2) R2 Gain-Max（AMP2）≦10 times(+20dB) AVREF 0.1F AVFRO (AMP4) R6 LGSX LINN (AMP3) Gain-Max（AMP3）≦10 times(+20dB) LVFRO (AMP5) Figure 3 Analog Interface PEDL7037-003-01Zz_Digest ML7037-003 A/D AVREF PGA D/A A/D PGA D/A 8/41 ...
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... When this is logic ‘0’, the AVREF pin is disabled (power-down state). When this is logic ‘1’, the AVREF pin is enabled, and the outputs of the AVREF, the AVFRO and the LVFRO become 1.4V approx.. This pin control is valid only during power-down. PEDL7037-003-01Zz_Digest ML7037-003 compliant (Please refer to SS2 9/41 ...
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... GND and between the XO and GND are influenced by load capacitance of a crystal unit and PCB patterns so that they are recommended to be determined by asking a crystal unit vendor for a matching test. XO MCK/XI R X’tal (12.288MHz) X'tal HC-49/U ex) Crystal Unit PEDL7037-003-01Zz_Digest ML7037-003 1M 10pF 10pF 10/41 ...
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... LSB PEDL7037-003-01Zz_Digest ML7037-003 LSB 11/ ...
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... The PCM coding format can be selected between 16-bit linear PCM (2’s complement) coding format and -law PCM coding format with the PCMSEL pin or the PCMSEL-bit [CR0-B4]. The PCM frame sync timing can be selected between a long frame sync and a short frame sync with the SYNCSEL pin. Refer Figure 5 to Figure8 for the timing. PEDL7037-003-01Zz_Digest ML7037-003 12/41 ...
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... Hi PEDL7037-003-01Zz_Digest ML7037-003 i D14 D13 D12 Hi D14 D13 ...
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... The single echo canceller mode should be selected in an environment where no line echoes exist. (Note) The change of the input state of this pin must be made during power-down state (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) or during initial mode. (Note) If this pin is not used, set this pin to a logic ‘0’. PEDL7037-003-01Zz_Digest ML7037-003 14/41 ...
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... PEDL7037-003-01Zz_Digest ML7037-003 GPIA1 GPIA0 Level (TPAD1) (TPAD0 +21dB 1 0 +18dB 0 1 +15dB 0 0 +12dB 1 1 +9dB 1 0 +6dB 0 1 +3dB 0 0 0dB 1 1 -3dB ...
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... DIN pin is an address and data input pin, the DOUT pin is a data output pin. If the mirrocontroller interface is not used, set the DEN pin to a logic “1”, the EXCK pin and DIN pins to a logic “0”, and the MCUSEL pin to logic ‘1’. Figure 9-12 shows the input/output timing. PEDL7037-003-01Zz_Digest ML7037-003 16/41 ...
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... PEDL7037-003-01Zz_Digest ML7037-003 ...
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... LSI behavior. (Note) The execution of this reset during a call may cause minor noises due to interruption at an arbitrary point in a sequence of PCM codes so that an execution of the reset is recommended to be made in a silent state. PEDL7037-003-01Zz_Digest ML7037-003 18/41 ...
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... OKI Semiconductor TSTI0, TSTI1, TSTI2 These are LSI manufacturer’s test input pins. Set these pins to a logic “0”. PEDL7037-003-01Zz_Digest ML7037-003 19/41 ...
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... DVDD x V Normal digital pins IH2 V MCK/XI IL1 V Normal digital pins IL2 t Digital pins IR t Digital pins IF 12.2867712 f MCK/XI MCK (-0.01%) d MCK/XI MCK PEDL7037-003-01Zz_Digest ML7037-003 Rating –0.3 to +4.6 –0.3 to +4.6 –0 +0.3 DD –0 +0.3 DD –20 to +20 350 –65 to +150 Min. Typ. Max. 3.0 3.3 3.6 3.0 3.3 3.6 -40 — 85 DVDD + — ...
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... SYNC f SYNC (* BCLK to SYNC (* SYNC to BCLK (* Digital pins DL C AVREF - AGND0 AVREF C VBG-DGND0 VBG C REGOUT0-DGND0 REGOUT1 C REGOUT1-DGND1 REGOUT2 PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit 64 —- 2048 kHz 128 — 2048 KHz 7.992 8.008 8.0 kHz (-0.1%) (+0.1%) 1BCLK — 100 µ ...
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... R Analog input pins (* AGSX0, AGSX1, LGSX L1 R AVFRO, LVFRO L2 C Analog output pins (* Analog output pins (*3) OF LVFRO, AVFRO V O RL=10k, Input=+3dBm0 PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit — 100 500 µA — 3.5 7.0 mA — — 0.02 10 µA -10 -0 ...
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... AVDD AVDDS t DVDD0,1 DVDDE t RSTS PDN t RSTW t RSTE t crystal unit (*1) SXO t SXO t RSTE Initial mode Normal Operation Figure 13 PDN, XO, AVREF Timing PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit 0 — — — — ns — — 100 ns 1.0 — — µs — — 250 ms — ...
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... PARW t PARH ｔ GPOD *2 ｔ GPOH t PARW t PARD Internal Process Data Address R Data t GPOD Geneal Purpose Output Port Pins PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit — — 250 µs 250 — — µs — — 250 µs — — 100 ns — ...
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... Linear PCM mode Short frame sync mode (*1, *2, *3) SYNC to BCLK (*3) BCLK to SYNC (*3) — — C =50pF DL C =50pF DL C =50pF DL C =50pF LSB PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit 63.36 64 64.64 kHz 126.72 128 129.28 kHz 7.92 8.0 8.08 kHz 24.85 25 25.15 % 12.35 12.5 12.65 % 12.35 12 ...
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... Linear PCM) Figure 18 PCM Output Timing (Short Frame Sync LSB XD3 LSB XD2 PEDL7037-003-01Zz_Digest ML7037-003 50% VDD 50% VDD 50% VDD LSB 50% VDD 50% VDD 50% VDD Hi-Z 50% VDD Hi-Z LSB 50% VDD 50% VDD ...
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... Figure 19 Write Timing i Figure 20 Read Timing PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. 20 — — 20 — — 50 — — 100 — — 50 — — 50 — — — — — — ...
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... Condition G against a set gain (*1) AC1 against an adjacent gain step G AC2 (*2) PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit 25 — — dB -0.15 — 0.25 dB Reference — -0.15 — 0 — 0 — -0.15 — ...
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... Line-side *3 ML7037 L.P.F. Analog Rin Rout 5kHz Line or Acoustic Echo Canceller Analog Level Meter Sout Sin Power supply voltag e : 3.30V CODEC Input Gain = 1 CODEC Output Gain = 1 PEDL7037-003-01Zz_Digest ML7037-003 Min. Typ. Max. Unit — 13 — Min. Typ. Max. Unit — 35 — — 30 — ...
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... APGA4 APGA3 - I/E I/E # LPGA4 LPGA3 - I/E I/E A13 A12 A11 I/E I/E I I/E I/E I/E D13 D12 D11 I/E I/E I I/E I/E I LHLD # LCLP I/E - I/E AHLD # ACLP I/E - I/E I/E I/E I NCTHR - - I/E PEDL7037-003-01Zz_Digest ML7037-003 R OPE_STAT PCMEN ECSEL R/W (MCUSEL R RPAD2 RPAD1 RPAD0 R/W I/E I/E I/E TPAD2 TPAD1 TPAD0 R/W I/E I/E I/E APGA2 APGA1 APGA0 R/W I/E I/E I/E LPGA2 LPGA1 LPGA0 R/W I/E I/E I/E A10 A9 A8 R/W I/E I/E I R/W I/E I/E I/E D10 ...
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... PEDL7037-003-01Zz_Digest ML7037-003 R AVFROS LVFROS # EL EL R/W - I/E I/E AATTMO AATTMO # DE1 DE0 R/W - I/E I/E LATTMO LATTMO # DE1 DE0 R/W - I/E I EQL_2 EQL_1 EQL_0 ...
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... When you write a control register in any other mode than the initial mode, SYNC signals (8kHz) must be supplied unless the ML7037-003 is in the internal clock mode (the CLKSEL pin = logic 0’). (Note) Refer to descriptions under Internal Data Memory Access for a way to set CR6, CR7, CR8 and CR9. ...
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... Figure 25 Micro Controller Interface Flow Chart Wait for 250ms (approx longer Yes CR1-B7="1" (Write) * CR1-B7 is automatically cleared af ter a completion of a write. No CR1-B7="0" (Read) Yes Yes Another Internal Data Memory Setting? No PEDL7037-003-01Zz_Digest ML7037-003 Internal Data Memory Access Initial Mode 33/41 ...
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... PDN pin or the SPDN-bit [CR0-B7], and the READY-bit [CR10-B7] turns logic ‘1’ which shows the ML7037-003 has got ready for the control register access. During this initial mode, specify both the 16-bit wide address by the CR6-CR7 and the 16-bit wide data by the CR8-CR9 first, and then write a logic ‘ ...
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... OKI Semiconductor PIN CONTROL AND CONTROL REGISTERS Some of functions and states with the ML7037-003 could be determined either by input state of certain pins (their secondary functions, if the pins are general-purpose input port pins) and/or the control registers. In such cases, the functions and states are determined by ORed logics between them. Hence, when a function or a state is determined (called as “ ...
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... VBG 150pF DGND0 DVDD1 REGOUT1 0.1μF DGND1 MCK/XI 12.288MHz XO : Analog : Differential : 16bit Linear PCM : Long frame sync : Internal clock mode (Clock master) : used Figure 27 PEDL7037-003-01Zz_Digest ML7037-003 BCLK (NC) SYNC (NC) PCMI PCMO (NC) GPIA0 GPIA1 GPIA2 GPIA3 GPIA4 GPIA5 GPIA6 GPIA7 GPIB0 GPIB1 GPIB2 ...
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... TSTI0 : Digital (PCM) : Single : µ-law PCM : Short frame sync : External clock mode (Clock slave) : used Figure 28 PEDL7037-003-01Zz_Digest ML7037-003 BCLK input （64kHz～ 8kHz Sync signal input Line-side PCM input Line-side PCM output Transmit-side volume control Receive-side volume control +3.3V 10kΩ ...
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... LSI through control register setting due to its limitation of the available pin count. Therefore, basically, this LSI is recommended to use in the External MCU Mode controlled with the TPAD, the RPAD, and/or the RALC. analog input (LINN) that is set at less than 1.3 VPP. PEDL7037-003-01Zz_Digest ML7037-003 38/41 ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code, and desired mounting conditions (reflow method, temperature and times). PEDL7037-003-01Zz_Digest ML7037-003 (Unit : mm) 39/41 ...
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... OKI Semiconductor REVISION HISTORY Document Date No. PEDL7037-003-01Zz Oct. 13, 2006 _Digest Page Previous Current Edition Edition – – First edition PEDL7037-003-01Zz_Digest ML7037-003 Description 40/41 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL7037-003-01Zz_Digest ML7037-003 Copyright 2006 Oki Electric Industry Co., Ltd. 41/41 ...