msm9225 Oki Semiconductor, msm9225 Datasheet
msm9225
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msm9225 Summary of contents
Page 1
... Semiconductor MSM9225 CAN (Controller Area Network) Controller GENERAL DESCRIPTION The MSM9225 is a microcontroller peripheral LSI which conforms to the CAN protocol for high-speed LANs in automobiles. FEATURES •Conforms to CAN protocol specification (Bosch Co., V.2.0 part b/Full CAN) • Maximum 1 Mbps real-time communication control (programmable) • ...
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... Bit timing logic (BTL) Data manege- Data ment memory logic Suspention CAN Seat-position controller CAN CAN Power window CAN Outside mirror controller MSM9225 Bit stream logic (BSL) Transmission Tx0 control logic Tx1 (TCL) Error management logic (EML) Receive Rx0 control logic ...
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... Semiconductor PIN CONFIGURATION (TOP VIEW SDO 5 GND 6 SDI 7 SCLK 8 PRD/SRW INT 11 44-Pin Plastic QFP MSM9225 33 AD2/D2 32 AD1/D1 AD0/ Mode1 29 Mode0 GND 28 PALE 27 PWR 26 RESET Tx1 3/73 ...
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... If the microcontroller's bus cycle is fast, a signal is output to extend the bus cycle until the internal access is completed. PRDY 16 O /SWAIT Parallel mode Serial mode Description Internal access in progress After completion of access "L" level output High impedance output "H" level output "L" level output MSM9225 4/73 ...
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... Internal logic GND pin. 28 — Power supply pin for receive input differential amplifier. DD AGND 17 — GND pin for receive input differential amplifier. Description Mode0 Interface 0 Parallel mode Separate buses 1 0 Multiplexed buses 1 Serial mode MSM9225 No address latch signal With address latch signal 5/73 ...
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... Message Message Message Message Message Message Message Message — — — Various control registers 1 1 MSM9225 IDFM = 1 (extended) Identifier 2 Identifier 3 Identifier 4 Message 0 Message 1 Message 2 Message 3 Message 4 Message 5 Message 6 Message 7 6/73 ...
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... EIT : Transmission completion interrupt enable EIR : Receive completion interrupt enable RCS : Receive status TRQ : Transmission request Not used MMA : Message memory access enable Reception Operate Operate Reading of received data Stop Stop Rewriting of control area Rewriting of control area Rewriting of transmission data MSM9225 Transmission 7/73 ...
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... If the data frame is automatically transmitted after remote frame reception, the ARES bit should be set to "1". At reset, the ARES bit is set to "0". Transmission Format Data frame Remote frame Transmission disable Data frame Remote frame Data frame Transmission disable Remote frame MSM9225 Receive Format 8/73 ...
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... For standard format (IDFM = 0), the higher 3 bits of the 11 bits are set. For extended format (IDFM = 1), the higher 3 bits (ID28 to ID26) of the 29 bits (ID28 to ID0) are set. At reset, these bits are undefined. LSB IDB26 : IDB27 : IDB28 : DLC0 : DLC1 : DLC2 : DLC3 : IDFM : Format setting MSM9225 Identifier Data length code 9/73 ...
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... For both, a maximum of 8 bytes of transmission/receive data can be stored, but the number of transmittable/receivable bytes must have been set by data length code. At reset, message content is undefined. The relationship between address and identifier bits for extended format (IDFM = follows: LSB IDB18 : IDB19 : IDB20 : IDB21 : IDB22 : IDB23 : IDB24 : IDB25 : MSM9225 Identifier 10/73 ...
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... IDB3 : IDB4 : IDB5 : IDB6 : IDB7 : IDB8 : IDB9 : LSB Not used (Don't care) Not used (Don't care) Not used (Don't care) Not used (Don't care) Not used (Don't care) Not used (Don't care) IDB0 : IDB1 : MSM9225 Identifier 2 Identifier 3 Identifier 4 11/73 ...
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... Not used (reserve area) 9EH TMN Communication message number register 9FH CANS CAN status register AEH TEC Transmission error counter AFH REC Receive error counter BEH BFH CEH CFH DEH Not used (reserve area) DFH EEH EFH FEH FFH MSM9225 Name 12/73 ...
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... When SYNC is "1", the synchronization edge is set at both the rising and falling edges of data. At reset, SYNC is set to "0". LSB INIT : Initialize TIRS : Transmission identifier retrieval Not used SYNC : Bit synchronization CANA : CAN write flag Transmission flag Receive flag Not used MSM9225 13/73 ...
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... LSB EINTT : Transmission interrupt output enable EINTR : Receive interrupt output enable EINTE : Error interrupt output enable Not used ITF : Transmission interrupt request flag IRF : Receive interrupt request flag IEF : Error interrupt request flag MEINT : Master interrupt control enable MSM9225 14/73 ...
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... When MEINT is "1", interrupt request control is enabled. At reset, MEINT is set to "0". MEINT 0 1 INT pin EINTT 0 ITF 1 EIT (each message) EINTR 0 IRF 1 EINTE EIR (each message) 0 IEF 1 Interrupt factor (An error occurs) MSM9225 Interrupt factor (transmission completion) Interrupt factor (reception completion) 15/73 ...
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... LSB BRP0 : BRP1 : BRP2 : BRP3 : BRP4 : BRP5 : SJWA : SJWB : MSM9225 LSB NMES0 Number of message · · · · Baud rate prescaler Synchronization Jump Width 16/73 ...
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... BRP4 + 2 ¥ BRP3 + SJW1, SJW2 1 ¥ BTL cycle 2 ¥ BTL cycle 3 ¥ BTL cycle 4 ¥ BTL cycle MSM9225 · · ¥ BRP2 + 2 ¥ BRP1 + BRP0 2 1 17/73 ...
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... BTL cycle 0 1 · · · · · · 15 ¥ BTL cycle ¥ BTL cycle 1 1 TSEG2 1 ¥ BTL cycle 0 2 ¥ BTL cycle 1 · · · · 7 ¥ BTL cycle 0 8 ¥ BTL cycle 1 MSM9225 Time segment 1 Time segment 2 18/73 ...
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... Semiconductor (3) Bit timing Bit timing is set by CAN bus timing registers 0 and 1. The relationship between 1 bit time of a message and a CAN bus timing (the MSM9225 register follows: SYNC-SEG PROP-SEG SJW1 (BTR0 : SJWB/A) 1BTL cycle If setting is : BTR0 = "01000001" ...SJWB = "0" SJWA = "1" BRP5-0 = "000001" ...
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... Output example 1 1 Data Tx0 Tx1 LSB OCMD0 : Output mode OCMD1 : OCPOL0 : OCTN0 : buffer format OCTP0 : OCPOL1 : OCTN1 : buffer format OCTP1 : Output mode of Tx0 and Tx1 MSM9225 setting Tx0 output Tx1 output 20/73 ...
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... The circuit configuration of the output driver and the relationship between bit content and output driver format are as follows: At reset, all bits are set to "0". Output data Synchronization clock Circuit configuration GND Output control circuit GND MSM9225 Tx0 Tx1 21/73 ...
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... MSM9225 off Floating off Floating off Floating off Floating on "0" off Floating off Floating on "0" off Floating off "1" off "1" off Floating on "0" ...
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... M0ID8 M0ID7 M0ID2 M0ID1 M0ID0 0 M1ID26 M1ID25 M1ID24 M1ID23 M1ID18 M1ID17 M1ID16 M1ID15 M1ID10 M1ID9 M1ID8 M1ID7 M1ID2 M1ID1 M1ID0 0 MSM9225 LSB GMR01 GMR00 GMR0 GMR11 GMR10 GMR1 LSB M0ID22 M0ID21 GMSK00 M0ID14 M0ID13 GMSK01 M0ID6 M0ID5 GMSK02 0 0 GMSK03 LSB ...
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... Stop mode: STOP If STOP is set to "1", the MSM9225 will enter the stop mode when the CAN bus is idle. In stop mode, the content of data memory is held but the oscillator and all circuits stop to save power consumption. Access to/from external units is therefore disabled. ...
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... And when an error occurs, the message number of the message being transmitted/received at that time is stored. This is a read-only register and is set to "0000" at reset. LSB TRSN0 : TRSN1 : TRSN2 : TRSN3 : Not used Not used Not used Not used MSM9225 Transmission message number register 25/73 ...
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... BUS OFF state. At reset or when TEP < 256, BOFF becomes "0". LSB REW : Receiver Error Warning REP : Receiver Error Passive Not used Not used TEW : Transmitter Error Warning TEP : Transmitter Error Passive BOFF : Bus OFF flag Not used MSM9225 26/73 ...
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... The relation between the Transmit Error Counter and TEC is shown below. Transmit Error 8 Counter BOFF (CANS: bit6) 1: Bus off state LSB TEC0 : TEC1 : TEC2 : TEC3 : TEC4 : TEC5 : TEC6 : TEC7 : TEC (AEh TEP (CANS: bit5) 0: Error active state 1: Error passive state MSM9225 Transmit Error Counter 27/73 ...
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... The relation between the Receive Error Counter and each register is shown below. Receive Error 7 Counter LSB REC0 : REC1 : REC2 : REC3 : REC4 : REC5 : REC6 : REC7 : REC (AFh REP (CANS: bit1) 0: Error active state 1: Error passive state MSM9225 Receive Error Counter 28/73 ...
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... Semiconductor OPERATIONAL DESCRIPTION MSM9225 operation is described below. Operational Procedure Procedures to set and operate various communication protocols are indicated below. 1. Initial setting The initial setting procedure is indicated below. Start initial setting Set INIT bit of CANC register (0Ehex) to "1" Read INIT bit ...
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... MMA = 0 and TRQ = 1 All transmit message settings complete? YES Set TIRS bit of CANC register (0Ehex) to "1" Transmit setting complete Transmission operation *) Since the MMA bit cannot be set to "1" while the message is being accessed, read and verify its value MSM9225 30/73 ...
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... Check whether new reception data has been written to the same message while data NO was being read. *) Check whether reception data has been written to another message while data was being read. This step may be omitted and evaluation performed based on the interrupt signal. MSM9225 31/73 ...
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... Start rewrite Set MMA bit of inside message control register (X0hex) to "1" Read MMA bit MMA = 1? NO YES Rewrite message unit FRM/DLC3-DLC0/ID28-ID0 Set MMA bit of inside message control register to "0" All message settings complete? NO YES Rewrite complete MSM9225 32/73 ...
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... EIR — 2 EIT 1 1 FRM 0 0 ARES 1 A flow chart of the operation is shown on the following page. Comments When reception is complete, TRQ bit changes from 0 Æ 1 Set transmit interrupt to verify the end of transmission. Set the remote frame. Set automatic response. MSM9225 33/73 ...
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... Remote transmission verification Set ITF bit to "0" Set RSC bit of inside message control register to "0" Figure: Automatic Response Operation Flow Chart MSM9225 operation NO Remote frame reception? YES Data frame transmission Transmission completion generates interrupt INT: 1 Æ 0 ...
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... A flow chart of the operation is shown on the following page. The basic operation is a combination of receive and transmit procedures. Comments Set to receive message. Set interrupt to verify (remote frame) reception. Set interrupt to verify the end of transmission. Set the remote frame. Specify that there will be no automatic response. MSM9225 35/73 ...
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... Set inside message control registers MMA = 0 and TRQ = 1 Set TIRS bit of CANC register (0Ehex) to "1" Remote transmission Verify transmission is complete Figure: Manual Response Operation Flow Chart MSM9225 operation Remote frame reception? YES Message reception generates interrupt INT: 1 Æ Data frame transmission ...
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... DLC is received and written to the message memory. When the received DLC does not match with the DLC being set to message memory, the MSM9225 operates as follows: (1) Received DLC > DLC on message memory The number of bytes of data indicated by the DLC on the message memory is received and written to the message memory ...
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... The range in which the same identifier is set MSM9225 38/73 ...
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... Next, input data to the SDI pin. An internal register captures data in a similar manner to the address capture, at the rising edge of SCLK. When 8 bits of data have been captured, the MSM9225 writes the data to the internal memory or register specified by the address that was received previously, and then increments the counter data written to consecutive addresses, continue the data transfer. After all data has been transferred, set the CS pin to a " ...
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Data write timing CS SCLK SDI (HiZ) SDO R/W WAIT Address reception (2) Data read timing CS SCLK SDI SDO * * * * * ...
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... Semiconductor Parallel Interface The following three types of parallel interfaces are available. (1) Address/data separate bus type, no address latch signal (2) Address/data separate bus type, with address latch signal (3) Multiplexed bus type For transfer timings, refer to the timing diagrams for electrical characteristics. MSM9225 41/73 ...
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... Semiconductor MSM9225 CONNECTION EXAMPLES Microcontroller Interface (1) Address/data separate bus (no address latch signal) Microcontroller INT WAIT 4-1, 44-41 A7-0 D7-0 RESET Reset signal (2) Address/data separate bus (with address latch signal) Microcontroller INT CS ALE RD WR WAIT 4-1, 44-41 A7-0 D7-0 RESET Reset signal +5 V MSM9225 11 INT PALE 9 PRD/SRW ...
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... SDI 8 SCLK Mode1 25 RESET Mode0 +5 V MSM9225 11 INT PALE 9 PRD/SRW 26 PWR 16 PRDY/SWAIT 4-1, 44-41 A7-0 38-31 AD7-0/D7-0 5 SDO 7 SDI 8 SCLK Mode1 25 RESET Mode0 MSM9225 CST16MXW040 self-excitation is used, in the same manner as for the separate bus, connect an external oscillator Open 30 29 43/73 ...
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... RxD 6N137 8 2 ANODE Open 5 GND 4 Open CATH O.P. TxD PCA82C250 5 Vref 4 RxD 1 TxD 470 MSM9225 124 0 GND 7 CANH 6 CANL 5 Vref Open 8 Rs 124 W 124 0 GND 7 CANH 6 CANL 124 W 44/73 ...
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... Semiconductor (3) Monitoring the CAN bus Battery + Rx1 18 MSM9225 Rx0 23 Tx1 Open 22 Tx0 Port Microcontroller Port Port GND 8 RTH 1 INH PCA82C252 11 3 CANH RxD 12 CANL 2 TxD 9 RTL 5 STB 4 NERR 6 EN MSM9225 45/73 ...
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... Overload frame : frame that is output when the receive side has not completed preparing for reception * In a wired-OR logic circuit, the stronger value is defined as "dominant" and the weaker value as "recessive". In figures hereafter, dominant (abbreviation and recessive (abbreviation MSM9225 46/73 ...
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... Even when the data length code of the control field is nonzero, there will be no data frame transfer. Data frame 4 5 Remote frame 3 5 MSM9225 Interframe space End-of-frame Ack field CRC field Data field Control field Arbitration field Start-of-frame ...
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... Notes: ID28 to ID0 is the identifier. The identifier is transmitted MSB first prohibited to set the identifier = 1111111XXXXX. Start-of-frame (Arbitration field) 1 bit (Control field) IDE r0 (r1) (1 bit) Arbitration field IDE Identifier ID17 ID0 (1 bit) (18 bits) (1 bit) MSM9225 (Control field) RTR r1 r0 48/73 ...
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... No. of bits Standard format mode 11 bits Extended format mode 29 bits RTR Bit Setting RTR bit Frame type Dominant Data frame Recessive Remote frame Mode Setting SRR bit IDE bit None Dominant Recessive Recessive Control field r0 DLC3 DLC2 DLC1 MSM9225 (Data field) DLC0 49/73 ...
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... DLC1 DLC0 • • • • • • Data field Data Data (8 bits) (8 bits) CRC field Ack field CRC sequence (15 bits) CRC delimiter (1 bit MSM9225 0 1 • • (CRC field) 50/73 ...
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... Ack field ACK slot Ack delimiter (1 bit) (1 bit) End-of-frame (7 bits) Interframe space Intermission Bus idle (0 to • bits) (3/2 bits) Interframe space Suspend transmission (8 bits) MSM9225 (Ebd-of-frame) (Interframe space or overload frame) (Each frame) (Each frame) Bus idle (0 to • bits) 51/73 ...
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... No transmit hold Reception is performed. Transmit hold Evaluated as a start-of-frame from own node. The identifier is transmit. Bus idle: State where bus is not being used by any node. Intermission Bit Length Protocol mode Bit length 3 bits Error Status and Operation Operation Operation MSM9225 52/73 ...
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... Outputs 8 consecutive "receive" bits. If the 8th bit is observed to be "dominant", an overload frame is transmit biginning at the next bit. Output following the bit in which an error occurred. (In the case of a CRC error, this field is output following the Ack delimiter.) "Interframe space" or "overload frame" continues. MSM9225 53/73 ...
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... Having received an "overload flag" during an "interframe space", node n outputs an overload flag. Outputs 8 consecutive "recessive" bits. If the 8th bit is observed to be "dominant", an overload frame is transmit biginning at the next bit. Output following end-of-frame, error delimiter, and overload delimiter. "Interframe space" or "overload frame" continues. MSM9225 54/73 ...
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... The sleep mode is released when the Rx0 and Rx1 differential inputs, the RESET pin input, or the CS pin input "L" level. The stop mode is released when the RESET pin input or the CS pin input "L" level. MSM9225 55/73 ...
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... Transmit/Receive Start-of-frame to CRC node saquence Receive node Start-of-frame to data field CRC delimiter • Ack field • End-of-frame Receive node • Error frame • Overload frame Transmit node Ack slot Output timing MSM9225 56/73 ...
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... Passive error flag 128 or greater (6 consecutive "recessive" bits) Communication not possible consecutive "recessive" bits occur 128 256 or greater times, then when the error counter = 0, the state can return to error active. — No bus OFF MSM9225 57/73 ...
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... After an error flag is output, the indicated values are added to the error counter. Transmit error counter Receive error counter No change +1 No change + change +8 No change No change + –1 No change (±0 when error counter = 0) (1) –1 (1 £ REC £ 127) No change (2) ±0 (REC = 0) (3) Set to 127 MSM9225 58/73 ...
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... Semiconductor 7. Baud rate control function (1) Prescaler The MSM9225 has a prescaler that divides the frequency of the system clock. The prescaler divides the system clock frequency by a factor generate clock CK Time Logic) (2) Bit timing The timing for 1 data bit is defined below. ...
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... The bit detected at the edge forces the sync segment, and is followed by the prop segment. The bit timing is restarted. Previous bits CAN bus Bit timing Sync segment Prop segment SJW Start-of-frame Phase Phase segment 1 segment 2 Later bits Phase Phase segment 1 segment 2 MSM9225 60/73 ...
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... Data field Complete Bit error CRC field Complete Ack error Ack field Complete Bit error End-of-frame Error frame Complete Complete Bit error Bit error Intermission 1 Overload frame Complete Error active Initial setting Bus idle Start-of-frame transmission MSM9225 Form error 61/73 ...
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... CRC field Complete Form error Bit error Ack field Complete Form error Bit error End-of-frame Preparation not complete Preparation Complete Complete Bit error Intermission 1 Complete Initial setting Bus idle Start-of-frame reception MSM9225 Error frame not Form error complete Overload frame 62/73 ...
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... TEC £ 255 Error passive TEC ≥ 256 TEC ≥ 256 Bus OFF 11 consecutive bits are "1", occurs 128 times TEC = 0 Error active 0 £ REC £ 127 REC ≥ 128 Error passive 128 £ REC £ 255 Reception successful REC = 127 MSM9225 63/73 ...
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... Condition 25° — I — £ 25°C D — OP — STG Condition Min 4 — –40 OP MSM9225 Rating Unit –0.3 to +7.0 V –0.3 to +7 –0 0 –0 0 615 mW –40 to +115 °C –65 to +150 °C Typ. ...
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... AV = 4 –40 to +115° Condition — — — — 4 –40 to +115° Condition I = –3 – MSM9225 Min. Max. Unit 0. 0 –0.3 +0. –1.0 +1.0 mA –25 –3 mA –1.0 +1.0 V – 1.0 — ...
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... AV = 4 –40 to +115° Condition Min — — — 167 — — — — — — — — — — — MSM9225 = 16 MHz) OSC Max Unit 10 — — ns — — — — — ...
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... RESET "H" Level Input Width t WRSTH RESET "L" Level Input Width t WRSTL INT "L" Level Output Width t WINTL (*) T = 1/f OSC ( 4 –40 to +115° Condition Min. — 62 — 5 — 5 — 32T MSM9225 Max. Unit — — ms — — ns 67/73 ...
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... Semiconductor TIMING DIAGRAMS Separate Bus Mode Read access timing CS A7-0 AD7-0/ D7 PRD/SRW PRDY/SWAIT Write access timing CS A7-0 AD7-0/ D7 PWR PRDY/SWAIT t cyc t RDH t RDLY t ARHDLY t ARLDLY t cyc t t WDS WDH t WRL t ARHDLY t ARLDLY MSM9225 t HRC t RAH t WRDH t HWC t WAH t WRH 68/73 ...
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... Read access timing CS t WALEH PALE t AS A7-0 AD7-0/ D7-0 PRD/SRW PRDY/SWAIT t ARLDLY Write access timing CS t WALEH PALE t AS A7-0 AD7-0/ D7 PWR PRDY/SWAIT t ARLDLY cyc t RAH t RDH t RDLY t ARHDLY t HWC t HWA t cyc t WAH t t WDS WDH t WRL t ARHDLY MSM9225 HRC HRA t WRDH t WRH 69/73 ...
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... Read access timing CS t WALEH PALE AD7-0/ D7-0 PRD/SRW PRDY/SWAIT t ARLDLY Write access timing CS t WALEH PALE AD7-0/ D7 PWR PRDY/SWAIT t ARLDLY t HRC t cyc t RDH t RDLY t ARHDLY t HWC t cyc t t WDS WDH t WRL t ARHDLY MSM9225 t HRA t WRDH t HWA t WRH 70/73 ...
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... RS PRD/SRW PRDY/SWAIT Write timing SCLK SDI (HiZ) SDO t RS PRD/SRW PRDY/SWAIT t WAIT DMY1 DMY6 DMY7 t t WRDY SRDLY t WAIT WRDY SRDLY MSM9225 t CH Don't Care CSZDLY 71/73 ...
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... Semiconductor Other Timings t WRSTL RESET t WINTL INT CLK (XT) t WRSTH t clkcy t clkcy MSM9225 72/73 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM9225 (Unit : mm) Package material Epoxy resin ...
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E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for ...