msm9225b ETC-unknow, msm9225b Datasheet - Page 4

• Manufacturer Part Number: msm9225b
• Description: Can Controller Area Network Controller
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS
1 Semiconductor
Symbol
SWAIT
AD7-0/
PALE
SCLK
PRDY/
D7-0
SRW
SDO
A7-0
PRD/
PWR
SDI
CS
41-44, 1-4
31-38
Pin
10
26
27
16
9
7
5
8
Type
I/O
O
O
I
I
I
I
I
I
I
Chip select pin. When “L”, PALE, PWR, PRD/SRW, SCLK and SDO
pins (microcontroller interface pins) are valid.
When “H”, these pins are invalid.
Address bus pins (when using separate buses). If used with a
multiplexed bus or if used in the serial mode, fix these pins at “H” or “L”
levels.
Multiplexed bus: Address/data pins (AD7-0)
Separate buses: Data pins (D7-0)
If used in the serial mode, fix these pins at a “L” levels.
Write input pin if used in the parallel mode. Data is captured when this
pin is at a “L” level.
If used in the serial mode, fix this pin at a “L” level.
Parallel mode: Read signal pin (PRD)
When at a “L” level, data is output from the data pins.
Serial mode: Read/write signal pin (SRW)
When at a “H” level, data is output from the SDO pin.
When at a “L” level, the SDO pin is at high impedance, and data is
captured beginning with the second byte of data input from the SDI pin.
Address latch signal pin
When at a “H” level, addresses are captured.
If used in the parallel mode and the address latch signal is unnecessary
or in the serial mode, fix this pin at a “H” or “L” level.
Serial data input pin
Addresses (1st byte) and data (beginning from the 2nd byte) are input to
this pin, LSB first. If used in the parallel mode, fix this pin at a “H” or “L”
level.
Serial data output pin
When the CS pin is at a “H” level, this pin is at high impedance. When
CS is at a “L” level, data is output from this pin, LSB first.
If used in the parallel mode, fix this pin at a “H” or “L” level.
Shift clock input pin for serial data
At the rising edge of the shift clock, SDI pin data is captured. At the
falling edge, data is output from the SDO pin.
Ready output pin
When required by the MSM9225B, a signal may be output to extend the
bus cycle until the internal access is completed.
Parallel mode
Serial mode
(SWAIT)
(PRDY)
Internal access in
“H” level output
“L” level output
progress
Description
After completion of
High impedance
“L” level output
access
output
FEDL9225B-03
MSM9225B
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