msm9810b Oki Semiconductor, msm9810b Datasheet - Page 4

• Manufacturer Part Number: msm9810b
• Description: 8-channel Mixing Oki Adpcm Type Voice Synthesis Lsi
• Manufacturer: Oki Semiconductor

PIN DESCRIPTIONS
OKI Semiconductor
30, 31, 33-38
40-47, 49-64
Pin
39
15
16
18
20
14
28
27
26
8
RA23-RA0
RD7-RD0
SERIAL
Symbol
D7/SD
D5/SO
D6/SI
CMD
ROE
RCS
WR
RD
CS
Type
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
Address pins for external memory. These pins become high impedance
when RCS pin is “H“.
Data pin for external memory. Pull-down resistors are internally
connected to these pins. These pull-down resistors become valid when
the RCS pin is “H”, and become invalid when the RCS pin is “L”.
Output enable pin for external memory.
When this pin is “L”, RA23 to RA0 and ROE pins output address data
and output enable signal.
When this pin is “H”, RA23 to RA0 and ROE pins become high
impedance.
Select pin for Command data or Subcommand data for CPU interface.
When this pin is “H”, subcommand input is selected.
When this pin is “L”, command input is selected. A pull-up resistor is
internally connected to this pin.
Read pin for CPU interface.
A pull-up resistor is internally connected to this pin.
Write pin for CPU interface.
A pull-up resistor is internally connected to this pin.
Chip select pin for CPU interface. When CS is “H”, WR/RD signal is not
entered in this LSI. A pull-up resistor is internally connected to this pin.
CPU input interface select pin. When SERIAL is “H”, serial input
interface is selected.
When it is “L”, parallel input interface is selected.
Data bus pin for CPU interface when parallel input interface is selected.
When WR is “L”, this pin serves as data input pin.
When RD is “L”, this pin serves as channel status data output pin.
When serial input interface is selected, this pin serves as serial data
input pin.
Data bus pin for CPU interface when parallel input interface is selected.
When WR is “L”, this pin serves as data input pin.
When RD is “L”, this pin serves as channel status output pin.
When serial input interface is selected, this pin serves as serial clock
input pin.
Data bus pin for CPU interface when parallel input interface is selected.
When WR is “L”, this pin serves as data input pin.
When RD is “L”, this pin serves as channel status output pin.
When serial input interface is selected, this pin serves as channel status
serial output pin.
Description
FEDL9810BFULL-03
MSM9810B
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