mt88e41as Zarlink Semiconductor, mt88e41as Datasheet - Page 6

• Manufacturer Part Number: mt88e41as
• Description: Cmos Extended Voltage Calling Number Identification Circuit Ecnic
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
In Europe, Caller ID and CIDCW services are being proposed. These schemes may be different from their North
American counterparts. In most cases, 1200 baud CCITT V.23 FSK is used instead of Bell 202. Because the ECNIC
can also demodulate 1200 baud CCITT V.23 with the same performance, it is suitable for these applications.
Although the main application of the ECNIC is to support CND and CIDCW service, it may also be used in any
application where 1200 baud Bell 202 and/or CCITT V.23 FSK data reception is required.
1.1
The input arrangement of the MT88E41 provides an operational amplifier, as well as a bias source (V
used to bias the inputs at V
for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 4.
Figure 3 shows the necessary connections for a differential input configuration.
1.2
The ECNIC provides a powerful 3-pin interface which can reduce the external hardware and software requirements.
The ECNIC receives the FSK signal, demodulates it, and outputs the extracted data to the DATA pin. For each
received stop bit start bit sequence, the ECNIC outputs a fixed frequency clock string of 8 pulses at the DCLK pin.
Each clock rising edge corresponds to the centre of each DATA bit cell (providing the incoming baud rate matches
the DCLK rate). DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data
into a peripheral device such as a serial to parallel shift register or a micro-controller. The ECNIC also outputs an
end of word pulse (data ready) at the DR pin. The data ready signal indicates the reception of every 10-bit word
sent from the Central Office. This output is typically used to interrupt a micro-controller. The three outputs together,
eliminate the need for a UART (Universal Asynchronous Receiver Transmitter) or the high software overhead of
performing the UART function (asynchronous serial data reception).
Note that the 3-pin interface may also output data generated by voice since these frequencies are in the input
frequency detection band of the device. The user may choose to ignore these outputs when FSK data is not
expected, or force the ECNIC into its powerdown mode.
1.3
For applications requiring reduced power consumption, the ECNIC can be forced into power down when it is not
needed to receive FSK data. This is done by pulling the PWDN pin high. In powerdown mode, the crystal oscillator,
op-amp and internal circuitry are all disabled and the ECNIC will not react to the input signal. DATA and DCLK are
at logic high, and DR and CD are at high impedance or at logic high when pulled up with resistors.The ECNIC can
be awakened for reception of the FSK signal by pulling the PWDN pin to ground (see Figure 9).
Input Configuration
User Interface
Power Down Mode
DD/2
. Provision is made for connection of a feedback resistor to the op-amp output (GS)
VOLTAGE GAIN
(A
Figure 4 - Single-Ended Input Configuration
V
C
) = R
F
/ R
R
IN
IN
R
F
V
GS
IN+
IN-
Ref
MT88E41
MT88E41
Ref
) which is
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