mt8870dsr1-1 Zarlink Semiconductor, mt8870dsr1-1 Datasheet - Page 14

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mt8870dsr1-1

Manufacturer Part Number
mt8870dsr1-1
Description
Integrated Dtmf Receiver With Enhance Sensitivity
Manufacturer
Zarlink Semiconductor
Datasheet

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AC Electrical Characteristics
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
2.
3.
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Used for guard-time calculation purposes only.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
With valid tone present at input, t
W
M
N
G
O
U
U
D
N
C
O
C
T
T
P
T
S
P
L
K
I
I
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up (Q to StD)
Propagation delay (TOE to Q
ENABLE)
Propagation delay (TOE to Q
DISABLE)
Power-up time
Power-down time
Crystal/clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
Characteristics
- V
DD
PU
=5.0V
equals time from PDWN going low until ESt going high.
±
MT8870D/MT8870D-1
5%, V
Zarlink Semiconductor Inc.
SS
=0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 10.
Sym.
DC
t
t
t
t
t
t
t
t
LHCL
HLCL
C
QStD
PStD
t
REC
REC
t
t
t
t
t
PTE
PTD
t
DO
PQ
DP
DA
PU
PD
f
ID
C
LO
14
CL
3.575
Min.
0.5
20
20
40
5
9
Typ.
3.579
300
3.4
12
50
30
20
50
11
4
8
5
3.583
Max.
110
110
8.5
14
40
40
16
60
30
11
1
Units
MHz
ms
ms
ms
ms
ms
ms
ms
ms
µs
µs
µs
pF
ns
ns
ns
ns
%
Note 1
Note 1
Note 2
Note 2
Note 2
Note 2
TOE=V
TOE=V
TOE=V
load of 10 kΩ,
50 pF
load of 10 kΩ,
50 pF
Note 3
Ext. clock
Ext. clock
Ext. clock
Conditions
Data Sheet
DD
DD
DD

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