92hd88b4x5ndg Integrated Device Technology, 92hd88b4x5ndg Datasheet - Page 21

• Manufacturer Part Number: 92hd88b4x5ndg
• Description: Single Chip Pc Audio System Codec+mono Speaker Amplifier+capless Hp+ldo
• Manufacturer: Integrated Device Technology

IDT PROPRIETARY / IDT
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
92HD88
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
2.10. Vendor Specific Function Group Power States D4/D5
2.9.1.
CONFIDENTIAL
Function
Port Presence Detect
state change
GPIO state change
The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the
system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using
D3 whenever there are no active streams or other activity that requires the part to consume full
power. The system remains in S0 during this time. When a stream request or user activity requires
the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To
enable this use model, the CODEC must resume within 10mS and not pop. Intel HDA ECR-15b /
Low Power White paper power goals are < 30mW when analog PC_Beep is not enabled, and <
60mW when analog PC_Beep is enabled. (Charge pump and BTL amplifier power excluded.)
While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3
state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-
ior is as follows (see the ECR15b section for more information):
AFG D3cold
The D3cold power state is the lowest power state available that does not use vendor specific verbs.
While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-
ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are
disabled. Per the HD Audio bus ECR 015b, the D3cold state is intended to be used just prior to
removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec
may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from
D3cold is less than 200mS.
The 92HD88 introduces vendor specific power states. A vendor defined verb is added to the Audio
Function Group that combines multiple vendor specific power control bits into logical power states
for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined
in the HD Audio specification and ECR15b. The Vendor Specific D4 state provides lower digital
power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-
ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-
log power consumption by turning off all analog circuitry except for reset circuits.
States D4/D5 are not entered until D3cold has been requested. Software can pre-program the D4 or
D5 state as a re-definition of how the part will behave when the D3cold power state is requested or
software may enter D3cold, then set the D4 or D5. The preferred method is to request D3cold, then
select D4 or D5 as desired.This will reduce the severity of pops encountered when entering D4 or
D5.
1.The Port Presence detect circuit is currently dependent on a clock and
must be changed to generate a wake event.
HDA Bus active
Unsolicited Response
Unsolicited Response
21
HDA Bus stopped
Wake Event
by an unsolicited
response
Wake Event followed by
an unsolicited response
92HD88
1
followed
PC AUDIO
V 0.94 07/11