92hd90 Integrated Device Technology, 92hd90 Datasheet - Page 276

• Manufacturer Part Number: 92hd90
• Description: Single Chip Pc Audio System Codec+speaker Amplifier+capless Hp+ldo+i2s
• Manufacturer: Integrated Device Technology

92HD90
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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Register Address
Register Address
Register Address
7.29.1.4. AIC3 Register.
7.29.1.5. PWRM Register.
7.29.1.6. RESET Register
7:6
5
4
3
2:0
7
6
5
4
3
2
1
0
7:0
Bit
Bit
Bit
RSVD
SAEN
AUXSWAP
MCLKMS
MCLK[2:0]
RSVD
RSVD
RSVD
HPPWD
SPKRON
DMICPWD
MCLKOut
RSVD
RESET
Label
Label
Label
RO
RW
RW
RW
RW
RO
RO
RO
RW
RW
RW
RW
RW
RW
Type Default
Type
Type Default
00
0
0
1
001
0
0
0
0
0
0
1
0
0
Default
276
Reserved
1 = Input enabled for I2S Secondary Audio
0 = Input disabled for Secondary Audio
Swap Left and Right Samples of Aux Audio Output.
0 = Left sample first in frame
1 = Right sample first in frame
MCLK master
0 = MCLK is an input
1 = MCLK is an output (not recommended in Aux Audio Mode
since 24/12MHz rates cant be supported and 112MHz internal
clock is imprecise but is useful for testing.)
MCLK rate
000 = 24MHz (HDA BitClk)
001 = 12MHz (HDA BitClk/2)
010 = 22.5792MHz
011 = 11.2896MHZ
100 = 5.6448MHZ
101 = 28.224MHz
110 = 14.112MHz
111 = 7.056MHz
Writing causes registers to revert to their default values (similar
to a function group reset)
BTL (port D) is forced on in Aux Audio Mode
DMIC powered down in Aux Audio Mode (including DAC)
Reserved
Reserved
Reserved
Reserved
Headphone ports are forced off in Aux Audio Mode (including
charge pump)
MCLK Output Enabler
0 = MCLK Output is disabled in master mode
1 = MCLK is an output in master mode (input in slave mode))
Description
Description
Description
V 0.91 10/10
92HD90