mt8941bpr1 Zarlink Semiconductor, mt8941bpr1 Datasheet - Page 16

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mt8941bpr1

Manufacturer Part Number
mt8941bpr1
Description
Advanced T1/cept Digital Trunk Pll
Manufacturer
Zarlink Semiconductor
Datasheet
Figures 11 and 12 show how the MT8941B can be used to synchronize the ST-BUS to the CEPT transmission link
at the master and slave ends.
Generation of ST-BUS Timing Signals
The MT8941B can source the properly formatted ST-BUS timing and control signals with no external inputs except
the crystal clock. This can be used as the standard timing source for ST-BUS systems or any other system with
similar clock requirements.
Figure 13 shows two such applications using DPLL #2. In one case, the MT8941B is in FREE-RUN mode with an
oscillator input of 16.384 MHz. In the other case, it is in NORMAL mode with the C8Kb input tied to V
applications, DPLL #2 does not make any corrections and therefore, the output signals are free from jitter. DPLL #1
is completely free.
Crystal Clock
(16.384 MHz)
Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link
MS0
MS1
MS2
MS3
F0i
C12i
EN
C8Kb
C16i
EN
EN
V
SS
CV
C4o
C2o
C
MT8941B
RST
V
C4b
C2o
F0b
DD
Y
Zarlink Semiconductor Inc.
o
R
MT8941B
V
DD
16
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
C2i
F0i
E8Ko
MH89790B
Mode of Operation for the MT8941B
OUTA
OUTB
DSTo
CSTo
CSTi0
CSTi1
DSTi
RxR
RxT
TRANSMIT
RECEIVE
MULTIPLEX
MT8980/81
PRIMARY
DIGITAL
SWITCH
ST-BUS
CEPT
LINK
Data Sheet
DD
. For these

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