mt8920bs1 Zarlink Semiconductor, mt8920bs1 Datasheet - Page 17

• Manufacturer Part Number: mt8920bs1
• Description: 32 Channels Tdm St-bus To Parallel Bus Access Circuit
• Manufacturer: Zarlink Semiconductor

AC Electrical Characteristics
(V
Data Sheet
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
††The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.
(1) t
(2) Worst case access when memory contention occurs.
† During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.
10
CC
1
2
3
4
5
6
7
8
9
testing.
or t
=5.0V
cwm
CLmin
Address to DS (CS) Low
R/W to DS (CS) Low
DS (CS) Low to DTACK Low
Valid Data to DTACK Low (Read)
DS High to DTACK High
DS High to Data High Imped.(Read)
DS High to CS High
Data Hold Time (Write)
Input Data Valid after DS
Address Hold Time
is equal to t
A0 - A5
CS (IACK
R/W
DS
DTACK
D0 - D7
D0 - D7
±
5%,T
=70ns.
A
=-40 to 85
Characteristics
†
CH
)
or t
°
C, V
CL
°
C)
whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having t
DD
††
=5V, t
††
††
CLK
=244 ns, t
t
RWDS
†
††
Figure 14 - Mode 1 Parallel Bus Timing
- Mode 1 Parallel Bus Timing (see Fig. 14)
CH
t
t
DST
ARDS
t
=t
t
t
RDS
Sym.
RWDS
t
t
ARDS
t
t
t
t
ADHT
CL
t
DHZ
CSH
DAR
DHT
DST
RD
t
ADHT
=122 ns and are for design aid only: not guaranteed and not subject to production
1,2
t
RDS
Min.
t
t
t
-30
cwm
cwm
RD
DATA IN
20
50
0
0
0
0
Typ.
t
CLK
t
DHT
‡
DATA OUT
2*t
Max.
t
cwm
-30
65
45
CLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load C
Load A, C
Load C, C
Load A, C
t
DHZ
Test Conditions
t
DAR
t
CSH
MT8920B
L
L
L
=130pF, R
=130pF, R
=50pF
CHmin
L
L
=740Ω
=740Ω
=70ns
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